Metal-Poly Gate LDMOS Structure for Resistive Path Alignment
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Solution Overview
Problem
The shrinking geometry sizes in semiconductor integrated circuits pose challenges for fabricating laterally diffused metal-oxide-semiconductor (LDMOS) transistors, particularly in achieving high resistive paths and accurate alignment due to shallow resistive paths and alignment issues in existing manufacturing processes.
Innovation Solution
A semiconductor device fabrication method involving the formation of first and second wells in a substrate, with different types of dopants, and the creation of dummy and poly gates with specific gate dielectric and electrode layers, followed by the replacement of dummy gate stacks with metal gate stacks, allowing for self-aligned source and drain regions and improved resistive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lightly doped source and drain regions are used to define the resistive path, then the LDMOS transistor can achieve high blocking voltage ability, but the resistive path becomes very shallow and may not offer sufficient resistance
Solution Approach 1:
The patent segments the gate structure into two distinct parts: a first gate (metal gate) and a second gate (poly gate). This segmentation allows independent optimization of each gate's function, enabling the first gate to control the resistive path depth while the second gate maintains blocking voltage capability, thus resolving the contradiction between sufficient resistance and manufacturing precision
Solution Approach 2:
The patent employs composite gate materials - combining metal gate (first gate) and poly gate (second gate) in a single device structure. The metal gate provides excellent electrical contact and control over the resistive path, while the poly gate contributes to high blocking voltage ability. This composite approach allows simultaneous achievement of both blocking voltage capability and sufficient resistive path depth
2Productivity
If geometry sizes continue to shrink, then functional density increases, but alignment and overlay control accuracy deteriorates
Solution Approach 1:
The patent introduces an intermediary structure - the first gate (metal gate) - that serves as a reference and alignment marker during fabrication. This metal gate structure provides distinct visual and physical markers that facilitate precise alignment of subsequent layers, including the second gate and source/drain regions, thereby maintaining alignment accuracy even as overall device dimensions shrink
Solution Approach 2:
The patent applies local quality by making the first gate have distinct material properties (metal) compared to the second gate (poly). This local differentiation creates clear boundaries and alignment references in critical areas, enabling precise overlay control for the second gate and surrounding structures, thus maintaining manufacturing precision despite reduced geometry sizes
3Manufacturing precision
If dummy gate stacks are replaced with metal gate stacks, then alignment accuracy and resistive path resistance improve, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by forming the first gate (metal gate) and its associated dielectric layer before forming the second gate (poly gate). This sequential approach with the first gate already in place provides a stable reference structure that simplifies subsequent alignment operations, reducing the actual complexity of the fabrication process despite the dual-gate structure
Solution Approach 2:
The first gate (metal gate) serves multiple functions: it acts as a functional gate controlling the channel, provides an alignment reference for the second gate, and defines the resistive path geometry. This multi-functionality reduces the need for separate structures, thereby offsetting the apparent complexity increase with functional consolidation
Data Source
AI summary
A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.