Integrated Metal-Poly Gate MOS Fabrication
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Solution Overview
Problem
The integration of polysilicon gate and metal gate MOS devices in integrated circuits poses challenges due to polysilicon depletion issues and increased manufacturing complexity and cost, requiring a simplified and cost-effective manufacturing scheme that addresses the electrical property changes and standard library rebuilds.
Innovation Solution
An integrated manufacturing process that forms I/O MOS devices with polysilicon gates and core MOS devices with metal gates on the same chip, using a semiconductor substrate with distinct gate dielectrics and electrodes, and includes the simultaneous formation of resistors and MOS capacitors with polysilicon gate electrodes, allowing for reduced complexity and cost by maintaining conventional standard libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal gate electrodes are used for core MOS devices to avoid poly depletion, then device performance is improved, but manufacturing complexity and cost increase due to separate processing requirements
Solution Approach 1:
The patent merges the formation of metal gate electrodes for core MOS devices with the formation of polysilicon gate electrodes for I/O MOS devices into a single integrated process. Both gate types are formed simultaneously using the same deposition and patterning steps, eliminating the need for separate processing sequences and reducing manufacturing complexity while maintaining the performance benefits of metal gates in core devices.
Solution Approach 2:
The patent creates a universal gate electrode formation process that can produce both metal gates and polysilicon gates using the same manufacturing steps. The process uses a common metal layer that can be selectively patterned to form metal gates in core regions while leaving polysilicon gates in I/O regions, making the manufacturing process adaptable to different device types without requiring separate process flows.
2Reliability
If I/O MOS devices use thick silicon oxides as gate dielectrics, then device reliability is improved, but integration with core MOS devices becomes complicated and costly
Solution Approach 1:
The patent implements local quality by depositing gate dielectric material with varying thicknesses in different regions of the substrate. Thick silicon oxide is deposited in I/O regions to provide high reliability, while thin silicon oxide is deposited in core MOS device regions to maintain performance. This spatial variation in dielectric thickness allows both I/O and core devices to have optimized characteristics without requiring separate processing lines.
Solution Approach 2:
The patent changes the physical parameter of gate dielectric thickness according to the device type. By controlling deposition conditions and using selective masking, the process achieves different oxide thicknesses (thick for I/O, thin for core) within the same processing sequence, enabling parameter-based differentiation without increasing integration complexity.
3Ease of manufacture
If all MOS devices are formed with metal gates simultaneously, then manufacturing cost is reduced, but electrical properties of associated devices change requiring standard library rebuilds
Solution Approach 1:
The patent segments the chip into core MOS device regions and I/O MOS device regions, allowing different gate electrode materials to be used in different segments. This segmentation enables the maintenance of conventional polysilicon gate I/O devices that are compatible with existing standard libraries, while simultaneously introducing metal gates in core regions for cost-effective manufacturing, thus avoiding the need for complete standard library rebuilds.
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.