Metal-Post Semiconductor Package for Low-Parasitic Interconnects
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Solution Overview
Problem
Semiconductor devices are highly sensitive to parasitic electrical effects such as parasitic interconnect resistance and capacitive coupling, which existing methods to mitigate often result in increased costs, larger package sizes, and reduced performance.
Innovation Solution
A method of forming a semiconductor package using a metal baseplate with metal posts, where a semiconductor die is mounted and encapsulated with an insulating mold compound, and the baseplate is removed to expose metal posts as package contacts, with conductive tracks formed using laser-activatable mold compound and plating processes to minimize parasitic effects while maintaining a small package footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods are used to reduce parasitic electrical effects, then device performance is improved, but package size increases and manufacturing cost increases
Solution Approach 1:
The patent extracts the base section of the leadframe from the final package structure, removing unnecessary metal material that would otherwise increase package size and parasitic effects. Only the essential metal posts remain to provide electrical connections, while the base section is selectively removed through chemical etching or mechanical processes.
Solution Approach 2:
The leadframe is segmented into distinct functional components: metal posts for electrical connections and the base section for structural support during manufacturing. This segmentation allows the base section to be removed after serving its purpose, reducing the final package size while maintaining manufacturing efficiency.
2Reliability
If conventional packaging methods are used to reduce parasitic electrical effects, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
The metal baseplate with integrated posts is provided as a pre-structured component before semiconductor die mounting. This preliminary structuring simplifies subsequent manufacturing steps and enables cost-effective production of low-parasitic packages.
Solution Approach 2:
The patent changes the physical and chemical parameters of the base section to enable selective removal. The base section is made of metal with specific etch selectivity relative to the posts, allowing chemical etching or mechanical removal processes to selectively eliminate the base section while preserving the posts, reducing material waste and manufacturing complexity.
3Reliability
If metal baseplate with posts is used, then parasitic electrical effects are reduced and package size is minimized, but manufacturing process complexity increases
Solution Approach 1:
The base section is designed with specific material properties (etch selectivity) that enable simple chemical or mechanical removal processes. This parameter optimization transforms a potentially complex selective removal operation into a straightforward manufacturing step.
Solution Approach 2:
The metal baseplate structure serves multiple functions: providing structural support during assembly, defining post positions, enabling selective removal, and facilitating thermal conduction. This multi-functionality reduces the need for additional components and simplifies the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic electrical effects at low cost and small package size, providing efficient electrical connections and thermal conduction paths while allowing for optical inspection features.
Implementation Method 1
forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section
Implementation Method 2
the forming conductive tracks comprises applying a laser to the second surface of the encapsulant body thereby forming a laser activated traces in the second surface of the encapsulant body
Implementation Method 3
performing an electroless plating process that forms seed layer parts of the conductive tracks, and performing an electroplating process that forms thicker metal layer parts of the conductive tracks
Implementation Method 4
providing efficient electrical connections and thermal conduction paths
Data Source
AI summary
A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.