Metal Power Rail Under Active Layer for Semiconductor Routing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The large size of power rails in semiconductor devices necessitates substantial area usage, reducing the space available for standard routing tracks or signal lines, which hampers the design and manufacture of integrated circuits.

Innovation Solution

A metal structure is positioned between the active layer and the substrate, extending across the widths of semiconductor fins and a separation distance between them, with isolation materials separating it from both the active layer and the substrate, allowing for electrical connection to epitaxial structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If power rails are implemented with larger sizes to supply power to multiple standard logic cells, then power supply capability is improved, but area available for routing tracks or signal lines is reduced

Engineering Contradiction:
Improvepower supply capabilityVSAvoidarea for routing tracks
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent moves the power rail from the traditional BEOL metal layer to a position beneath the active device layer, effectively utilizing the vertical dimension. This allows the power rail to extend across multiple fins without consuming horizontal routing area, as it is positioned in the depth dimension rather than competing for surface space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The power rail is nested beneath the active device layer and epitaxial structures, placing it within the vertical stack rather than adjacent to it. This nesting approach allows the power rail to coexist with other device components in the same vertical column, maximizing area utilization.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Power

If power rails are fabricated in back-end of line (BEOL) metal layers, then power distribution is achieved, but device height and routing density are reduced

Engineering Contradiction:
Improvepower distributionVSAvoiddevice height
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

Instead of placing the power rail in the conventional BEOL metal layer above the active devices, the patent inverts the approach by positioning the power rail beneath the active device layer. This inversion eliminates the need for additional BEOL metal layers dedicated to power distribution, thereby reducing overall device height.

Inventive Principle:
Principle #13The other way round (Inversion)

3Productivity

If metal structure extends across separation distance between fins, then signal routing density is improved, but isolation requirements increase

Engineering Contradiction:
Improvesignal routing densityVSAvoidisolation requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The metal structure serves multiple functions simultaneously: it acts as a power rail for power distribution, a ground rail for reference potential, and a routing line for signal transmission. This multi-functionality reduces the need for separate dedicated structures for each function, simplifying the overall device architecture despite the extended coverage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11217533B2Semiconductor device with metal structure under an active layer
Publication Date: 2022.01.04 GLOBALFOUNDRIES US INC
  • US11217533B2 patent drawing
  • US11217533B2 patent drawing
  • US11217533B2 patent drawing

AI summary

A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.