Metal Programmable Logic Multiple Function Pin Interface
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Solution Overview
Problem
Existing multiple function pin interfaces (MFPIs) face challenges in efficiently reconfiguring pin connections due to complex multiplexing systems, which limits adaptability to different usage models and increases design complexity, especially when dealing with larger numbers of function-in and function-out signals.
Innovation Solution
The implementation of a connection box with shorting bars that electrically interconnect core pins and multiple function pin interfaces (MFPIs) allows for flexible and programmable pin configurations, enabling easy re-design of chip connections based on usage models by altering the shorting bar connections, rather than reconfiguring multiple multiplexers and demultiplexers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multiplexing system with multiple multiplexers and demultiplexers is used to achieve multiple function pin interface, then pin count is reduced, but device complexity and design difficulty increase significantly
Solution Approach 1:
The patent extracts the complex multiplexing logic from the core chip design and relocates it to external programmable logic devices or configuration memory. This removes the burden of complex timing priority circuits, multiplexer/demultiplexer arrays, and associated control logic from the chip itself, while still achieving the pin reduction benefit through software-configurable pin assignment.
Solution Approach 2:
The patent introduces an intermediary layer (programmable logic device or configuration memory) that sits between the chip pins and the internal logic. This intermediary handles the complex routing and multiplexing functions externally, allowing the chip to maintain simple physical pin connections while achieving flexible multiple-function capability through software configuration.
2Adaptability or versatility
If differential timing priority is implemented in multiplexing system to handle multiple function-out signals, then signal routing flexibility is improved, but design complexity and timing issue management increase
Solution Approach 1:
Instead of implementing complex hardware-based timing priority management within the chip's multiplexing system, the patent inverts the approach by using software or programmable logic to handle routing decisions. This reverses the traditional hierarchy where hardware dictated timing priorities, allowing flexible reconfiguration without redesigning the entire multiplexing architecture.
Solution Approach 2:
The patent makes the pin assignment and signal routing dynamically reconfigurable through software or programmable logic, rather than being fixed in hardware. This allows the system to adapt to different timing priority requirements and usage models by loading different configuration data, eliminating the need for complex static timing priority circuits.
3Manufacturing precision
If chip is designed for specific usage model with fixed pin assignments, then manufacturing precision is maintained, but adaptability to different usage models decreases
Solution Approach 1:
The patent performs preliminary action by pre-establishing the physical pin connections and basic I/O pad structures during manufacturing with high precision. The specific pin assignments and routing configurations are then determined later through software configuration or programmable logic, allowing the same physically precise chip to be adapted to multiple usage models without remanufacturing.
Data Source
AI summary
Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed.