Metal Sealed Wafer Level CSP Waterproofing
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Solution Overview
Problem
Conventional wafer level chip size packages (CSPs) face waterproofing issues due to water penetration through interfaces between resin insulating films and semiconductor substrates, leading to corrosion of multi-layered wirings, and challenges in forming through electrodes and isolation structures in thick silicon substrates.
Innovation Solution
A semiconductor device design featuring a semiconductor substrate with a dicing region and a chip region, including a through isolation structure and peripheral wiring that surrounds the chip wiring, with a metal film formed on top and lateral sides of the wiring insulating film to prevent water penetration and enhance mechanical strength, allowing for thinning of the substrate and reduced aspect ratio of through electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a resin insulating film is used to seal multi-layered wirings, then the device can be manufactured with standard processes, but water penetrates through interfaces causing corrosion and reliability issues
Solution Approach 1:
The patent uses a composite sealing structure combining resin insulating film and metal film. The resin film provides baseline sealing and electrical insulation, while the metal film layer deposited on top and lateral surfaces provides enhanced water barrier protection. This composite approach leverages the advantages of both materials to achieve both manufacturability and improved waterproofing.
Solution Approach 2:
The patent employs thin film technology by depositing a metal film layer on the resin insulating film. This thin metal film acts as an additional barrier against water penetration through the sealing structure, providing enhanced protection while maintaining the overall compact design and not significantly increasing device thickness.
2Reliability
If a metal film is added to cover the resin insulating film, then waterproofing is improved, but water can still penetrate through the interface between metal film and semiconductor substrate
Solution Approach 1:
The patent extends the metal film sealing not only on the top surface but also on the lateral sides of the resin insulating film. This multi-dimensional coverage approach blocks water penetration paths from both above and the sides, preventing water from reaching the metal film-substrate interface and solving the remaining waterproofing issue.
3Strength
If a thick silicon substrate is used, then mechanical strength is sufficient for handling, but forming through electrodes and isolation structures becomes difficult due to high aspect ratio
Solution Approach 1:
The patent performs substrate thinning before forming the through electrodes and isolation structures. By reducing the substrate thickness in advance, the aspect ratio of the through electrodes is reduced, making the filling process easier and more reliable. The metal film sealing structure provides mechanical support during this thinning process.
Solution Approach 2:
The metal film sealing structure acts as an intermediary support element during substrate thinning. It provides mechanical strength to the thinned substrate, enabling handling and processing that would otherwise be difficult or impossible with such a thin substrate. This mediator allows the substrate to be thin enough for easy through-electrode formation while still maintaining sufficient mechanical integrity.
Data Source
AI summary
A semiconductor device comprising: (a) a semiconductor substrate having a dicing region circumscribing a chip region, the chip region including a central region and a peripheral region around the central region; (b) an active electrical structure formed to extend from a first main surface to a second surface vertically spaced apart from the last main surface in the central region of the semiconductor substrate; (c) a through dummy isolation structure formed within the peripheral region to extend from the first main surface of the semiconductor substrate to a third surface vertically spaced apart from the first main surface of the semiconductor substrate, the through dummy isolation structure surrounding the active electrical structure; (d) an insulating layer disbursed throughout the active electrical structure within the central region and around the through dummy isolation structure of the peripheral region, the insulating layer including top and opposed peripheral sides; and (e) a metal film located over the top and peripheral sides of the wiring insulating film and over the semiconductor substrate.