Metal Sections in Dielectric Layer for Power Distribution
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Solution Overview
Problem
Shrinking device sizes in semiconductor devices lead to increased resistance and power consumption, causing voltage drops and reliability issues in power distribution networks, which can result in decreased switching speeds and noise margins, and potential functional failures due to high current densities and electromigration.
Innovation Solution
Adding metal sections in a dielectric layer under a routed metal layer above an active device layer, without electrical connection to the local interconnect layer, to decrease resistivity and increase current capacity while preventing shorting of interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes and conductor sizes are shrunk to increase component density, then the density of components is improved, but the resistance increases and electrical performance deteriorates
Solution Approach 1:
The patent introduces an additional metal layer (M2) between the active device layer and the first routed metal layer (M1). This adds a vertical dimension to the power distribution network, allowing current to flow through multiple layers and reducing the resistance burden on any single layer, thereby maintaining electrical performance while enabling higher component density
Solution Approach 2:
The patent creates a composite power distribution structure by combining the active device layer, dielectric layer, second metal layer (M2), and first metal layer (M1) into an integrated multi-layer system. This composite structure distributes current across multiple conductive paths, reducing overall resistance and improving electrical performance without increasing device footprint
2Productivity
If conductor sizes are reduced to increase density, then component density is improved, but power consumption increases due to increased resistance
Solution Approach 1:
By adding the M2 layer vertically between the active devices and M1 layer, the patent creates additional current pathways that reduce resistance. Lower resistance directly reduces I²R power losses, allowing the system to maintain high component density without excessive power consumption penalties
3Productivity
If conductor sizes are reduced to increase density, then component density is improved, but heat generation increases due to increased resistance
Solution Approach 1:
The multi-layer structure with M2 inserted vertically distributes heat generation across multiple layers and conductive paths. This spatial distribution reduces localized heat concentration and improves thermal management, enabling high density without excessive heat generation
4Area of stationary object
If metal layers are minimized to reduce area, then area usage is improved, but voltage regulation precision deteriorates due to wide fluctuations in power demand
Solution Approach 1:
The patent uses the vertical dimension to add the M2 layer, creating a multi-layer power distribution network that can handle fluctuating power demands more effectively. This layered structure provides redundant current paths and reduces IR drops, improving voltage regulation precision without requiring larger metal layer areas
Solution Approach 2:
The composite multi-layer structure combines multiple conductive layers with dielectric separation, creating a robust power distribution system that maintains voltage regulation precision under varying load conditions while using minimal area
5Ease of operation
If package lead inductance is present to supply current to pads, then current supply is enabled, but voltage drop occurs at pad locations due to time-varying current
Solution Approach 1:
By introducing the M2 layer vertically between the active devices and M1 layer, the patent reduces the current burden on package leads and pad structures. The multi-layer internal distribution reduces the time-varying current demand at any single location, thereby reducing di/dt drops at pad locations while maintaining current supply capability
Data Source
AI summary
Certain aspects of the present disclosure provide apparatus and techniques for fabricating a semiconductor device. A semiconductor device includes: an active device layer a local interconnect layer disposed above the active device layer; a dielectric layer disposed above the local interconnect layer; a metal layer disposed above the dielectric layer; and one or more metal sections disposed in the dielectric layer underneath one or more metal regions of the metal layer, wherein none of the one or more metal sections is electrically connected to a trace in the local interconnect layer.