Metal Seed Layer Deposition for Semiconductor Recessed Features

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Solution Overview

Problem

As integrated circuit features shrink, depositing continuous metal seed layers becomes increasingly challenging, particularly in Damascene processing, leading to issues with void formation and terminal effects during electroplating.

Innovation Solution

A method involving the sequential deposition and redistribution of metal layers using iPVD sputtering and resputtering techniques to achieve improved step coverage and conformality of seed layers, with aggressive redistribution and additional flash layers to ensure adequate coverage and thickness, particularly in recessed features like vias and trenches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a single layer of metal is deposited to cover recessed features, then the deposition process is simple and fast, but the sidewall coverage is insufficient and voids form in interconnects

Engineering Contradiction:
Improvesidewall coverageVSAvoiddeposition process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The deposition process is divided into multiple sequential steps: initial deposition to fill recessed features, redistribution to improve sidewall coverage, and flash layer deposition to ensure complete coverage. This segmentation transforms a single complex deposition into manageable stages, each optimizing specific aspects of seed layer quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs preliminary redistribution of the initially deposited metal layer before final flash layer deposition. This preliminary action ensures that subsequent layers are deposited on an optimized substrate, improving overall sidewall coverage and preventing void formation in interconnects.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If thin seed layers are used in electroplating, then the fabrication process is faster and material usage is reduced, but terminal effects occur and reliability decreases

Engineering Contradiction:
Improvefabrication speedVSAvoidinterconnect reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The invention changes the physical and chemical parameters of the seed layer through controlled deposition and redistribution processes. By optimizing thickness, uniformity, and material distribution, the seed layer achieves adequate conductivity for electroplating while maintaining reliability and preventing terminal effects.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The method performs preliminary optimization of the seed layer through redistribution and flash layer deposition before the electroplating process. This ensures the seed layer has sufficient thickness and uniformity to support reliable electroplating, eliminating terminal effects while maintaining fabrication efficiency.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If aggressive metal redistribution is performed to improve sidewall coverage, then step coverage is enhanced, but material is removed from bottom portions of recessed features

Engineering Contradiction:
Improvestep coverageVSAvoidmetal material at recess bottoms
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The redistribution process is designed to be spatially selective, aggressively redistributing metal from field regions and top surfaces while preserving material at the bottom portions of recessed features. This local quality approach ensures sidewall coverage is improved without compromising the metal quantity needed at critical recess bottoms.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The flash layer deposition serves as a preliminary corrective action after redistribution. It replenishes any metal removed from recess bottoms during redistribution, ensuring both improved sidewall coverage and adequate material presence at feature bottoms before final electroplating.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in improved resistance characteristics, reduced void formation, and increased reliability of interconnects, along with enhanced fabrication yield by ensuring continuous and uniform seed layer coverage.

Implementation Method 1

depositing a first layer of metal on at least the bottom portions of the recessed features and on the field region

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 2

subsequently redistributing the deposited metal on the wafer, at least from the bottom portions of the recessed features to the sidewalls of the recessed features

Methodology Applied
Scientific EffectResputtering: Sputtering

Data Source

PatentUS7682966B1Multistep method of depositing metal seed layers
Publication Date: 2010.03.23 NOVELLUS SYSTEMS INC
  • US7682966B1 patent drawing
  • US7682966B1 patent drawing
  • US7682966B1 patent drawing

AI summary

Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.