Metal Select Gate Flash Memory Cell With High-K Dielectric
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Solution Overview
Problem
As flash memory cells shrink in size, the thinning of silicon dioxide as a gate dielectric leads to increased oxide leakage current, compromising the select gate current drive and overall performance.
Innovation Solution
The use of a metal select gate and a high K insulating material, such as HfO2, ZrO2, or TiO2, in conjunction with silicon dioxide, to enhance the select gate current drive and reduce leakage current, while maintaining the structure of a floating gate, control gate, and erase gate in non-volatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If silicon dioxide thickness is reduced to increase gate capacitance, then gate capacitance increases for higher current drive, but oxide leakage current increases significantly
Solution Approach 1:
The patent uses a composite gate dielectric structure comprising multiple layers: a first dielectric layer (silicon dioxide) directly on the substrate, a second dielectric layer (high-k material such as HfO2, ZrO2, or TiO2) on the first dielectric layer, and a third dielectric layer (silicon dioxide) on the second dielectric layer. This composite structure combines the benefits of different materials to achieve both high capacitance and low leakage current.
Solution Approach 2:
The patent changes the dielectric constant parameter by introducing high-k materials (HfO2, ZrO2, TiO2) with dielectric constants significantly higher than silicon dioxide. This allows achieving the required gate capacitance with a thicker effective dielectric layer, thereby reducing leakage current while maintaining or enhancing current drive capability.
2Power
If select gate oxide is reduced below 2 nm to increase gate capacitance, then current drive capability improves, but leakage current increases significantly
Solution Approach 1:
The patent replaces the single-layer thin oxide structure with a multi-layer composite dielectric structure incorporating high-k materials. This composite structure provides equivalent or higher capacitance without requiring the oxide thickness to be reduced below 2 nm, thereby maintaining reliability and reducing leakage current.
Solution Approach 2:
The high-k dielectric layer acts as an intermediary between the substrate and the control gate, providing the necessary capacitance enhancement while preventing direct tunneling leakage that occurs in ultra-thin oxide structures. The high-k material mediates the electrical field while maintaining lower leakage characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance and reduces leakage current, enhancing the speed and reliability of the memory cells by increasing the select gate current drive and maintaining control over the gate dielectric properties.
Implementation Method 1
a layer of silicon dioxide and a layer of high K insulating material
Implementation Method 2
the select gate being formed of a metal material
Data Source
AI summary
A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.