Metal-Semiconductor Alloy Control Gates for 3D Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional non-volatile memory devices, such as vertical NAND strings, face challenges in efficiently forming control gate electrodes with optimal metal-semiconductor alloy regions to enhance memory stack structures and electrical conductivity.
Innovation Solution
A method of forming a stack of alternating insulating and sacrificial material layers over a substrate, replacing sacrificial layers with electrically conductive layers, and appending each conductive layer with a metal-semiconductor alloy region to directly contact the memory stack structures' sidewalls, thereby forming effective control gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control gate electrodes are formed using conventional metal layers only, then the manufacturing process is simple, but the electrical conductivity and interface quality with memory stack structures are insufficient
Solution Approach 1:
The control gate electrode is formed as a composite structure comprising a metal layer and a metal-semiconductor alloy layer. The metal layer provides structural integrity and conductivity, while the metal-semiconductor alloy layer (e.g., TiSi2, CoSi2, NiSi2) forms a low-resistance Schottky contact with the memory stack structures, thereby enhancing overall electrical conductivity and interface quality.
Solution Approach 2:
The metal-semiconductor alloy region is selectively formed only at specific locations where the control gate electrode contacts the memory stack structures (e.g., at the sidewalls or interfaces). This localized alloy formation optimizes the contact quality at critical interfaces while maintaining the simplicity of the overall control gate structure in non-critical regions.
2Reliability
If metal-semiconductor alloy regions are appended to control gate electrodes, then the electrical conductivity is improved, but the manufacturing process complexity increases
Solution Approach 1:
The metal layer is deposited first as a sacrificial or precursor layer, and then the metal-semiconductor alloy layer is formed on top of it. The alloy layer is subsequently patterned and etched back to leave the alloy only at the desired contact regions with the memory stack structures. This preliminary deposition and selective removal approach simplifies the overall manufacturing by using standard deposition and etching processes in sequence.
Solution Approach 2:
The metal-semiconductor alloy layer is formed as a continuous layer initially, then excess alloy material is removed through etch-back or planarization processes. This leaves the alloy only where needed at the control gate-memory stack interface, extracting unnecessary material while maintaining the desired local alloy regions for optimal electrical contact.
3Reliability
If control gate electrodes directly contact memory stack structures, then the electrical performance is enhanced, but the manufacturing precision requirements increase
Solution Approach 1:
The metal-semiconductor alloy layer acts as an intermediary between the metal control gate electrode and the memory stack structures. This alloy layer provides a graded transition in material properties and creates a large-area contact interface, which reduces the sensitivity to alignment errors and ensures reliable electrical contact even with moderate manufacturing precision.
Solution Approach 2:
The formation of the metal-semiconductor alloy changes the physical and chemical parameters at the interface, including work function, contact resistance, and adhesion properties. These parameter changes enable better electrical contact and reduce the impact of dimensional variations, thereby lowering the effective manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of efficient memory devices with improved electrical conductivity and enhanced memory stack structures, addressing the limitations of existing technologies in forming effective control gate electrodes.
Implementation Method 1
metal-semiconductor alloy region comprising an alloy of the first metal and a semiconductor material
Implementation Method 2
appending each electrically conductive layer with a metal-semiconductor alloy region
Data Source
Figure 1
Figure 2A~3B
Figure 4A~5B
AI summary
An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.