Metal Semiconductor Compound Bit Lines for Vertical GAA Transistors
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Solution Overview
Problem
The increasing integration density of dynamic memory in semiconductor structures requires improved electrical performance of small-sized functional devices, particularly with vertical gate-all-around (GAA) transistors, where bit lines made of silicon cause significant resistance due to their composition.
Innovation Solution
A semiconductor structure with bit lines made of a metal semiconductor compound and vertically stacked GAA transistors, featuring a junctionless transistor design with doped regions, dielectric layers, and insulating layers to reduce resistance and enhance integration density and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical GAA transistors are used to improve integration density, then the area occupied by transistors increases to 4F2, but the bit lines made of silicon cause large resistance
Solution Approach 1:
The patent changes the material parameter of bit lines from silicon to metal semiconductor compound, which fundamentally alters the electrical resistance characteristic. This parameter change resolves the contradiction by maintaining high integration density while improving electrical performance through lower resistance bit lines.
Solution Approach 2:
The patent uses metal semiconductor compound as a composite material for bit lines, combining metal and semiconductor properties. This composite material provides both the low resistance needed for electrical performance and the compatibility with existing semiconductor fabrication processes, thereby resolving the contradiction between integration density and electrical performance.
2Ease of manufacture
If bit lines are made of silicon to maintain material compatibility, then manufacturing is easier, but resistance becomes large
Solution Approach 1:
The patent changes the material composition parameter of bit lines from pure silicon to metal semiconductor compound. This parameter change reduces resistance while maintaining compatibility with semiconductor fabrication processes, as the metal semiconductor compound can be integrated into existing CMOS工艺流程.
Solution Approach 2:
The patent adopts metal semiconductor compound which can be formed using standard semiconductor manufacturing techniques such as atomic layer deposition (ALD) and rapid thermal annealing (RTA). These are established, cost-effective processes that make the transition to metal semiconductor compound bit lines economically viable despite the material change.
3Device complexity
If traditional transistor design is used to simplify structure, then device complexity is reduced, but threshold voltage drift and leakage current occur
Solution Approach 1:
The patent extracts the gate structure from the traditional planar transistor configuration and removes it from surrounding the channel. This extraction simplifies the transistor structure by eliminating the complex gate-all-around geometry while maintaining reliable electrical characteristics through the junctionless design with uniform doping.
Solution Approach 2:
The patent inverts the traditional transistor design approach by using a junctionless structure with uniform doping throughout the channel, rather than using doped source/drain regions with a gate in between. This inversion eliminates threshold voltage drift and leakage current issues while maintaining structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of metal semiconductor compound bit lines and junctionless transistor design reduces resistance and contact resistance, improving the electrical performance and integration density of the semiconductor structure while avoiding issues like threshold voltage drift and leakage current.
Implementation Method 1
a material of the bit line including a metal semiconductor compound
Implementation Method 2
the semiconductor channel including a first doped region, a channel region and a second doped region arranged in sequence
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; bit lines, located on the base, and a material of the bit line including a metal semiconductor compound; semiconductor channels, each including a first doped region, a channel region and a second doped region arranged in sequence, and the first doped region being in contact with the bit line; a first dielectric layer, covering sidewall surfaces of the first doped regions, and a first interval being provided between parts of the first dielectric layer covering sidewalls of adjacent first doped regions on a same bit line; an insulating layer, covering sidewall surfaces of the channel regions; word lines, covering a sidewall surface of the insulating layer away from the channel regions, and a second interval being provided between adjacent word lines.