Metal Silicide Interconnects for 3D NAND Memory Area Reduction
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Solution Overview
Problem
Current 3D stacked non-volatile memory devices face challenges in reducing size and optimizing the use of space for interconnects and peripheral circuitry, leading to inefficiencies in signal routing and increased peripheral area requirements.
Innovation Solution
The implementation of metal silicide interconnects and the use of slits and memory holes to connect lower and upper metal layers efficiently, allowing for space-saving configurations and reduced peripheral area usage by eliminating the need for transfer and hookup areas between subarrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional interconnect structures are used with separate transfer and hookup areas, then signal routing can be achieved, but the peripheral area is excessively large
Solution Approach 1:
The patent combines the transfer area and hookup area into a single integrated interconnect structure. The metal silicide interconnect formations serve dual purposes: transferring signals between subarrays and providing hookup connections, thereby eliminating the need for separate dedicated areas and reducing overall peripheral space requirements.
Solution Approach 2:
The interconnect structures are designed to perform multiple functions simultaneously. The same metal silicide formations used for signal transfer between subarrays also serve as hookup connections to peripheral circuitry, making the interconnect system universal and eliminating redundant structures.
2Device complexity
If more peripheral area is allocated for interconnects, then signal routing can be simplified, but the memory device size increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By forming metal silicide interconnects at multiple vertical levels and utilizing vertical vias, the design achieves complex signal routing functionality without proportionally increasing the horizontal footprint of the memory device.
Solution Approach 2:
The interconnect structures are nested within the vertical stack of the memory device. Multiple interconnect layers are positioned at different heights within the same lateral footprint, allowing complex routing functionality to be packed into a compact vertical space rather than requiring expanded horizontal area.
3Use of energy by moving object
If conventional metal interconnects are used, then manufacturing can be straightforward, but capacitive loading is high
Solution Approach 1:
The patent changes the material parameter from conventional metal to metal silicide for the interconnect formations. This material substitution reduces capacitive loading due to the lower capacitance characteristics of silicide materials, while the formation process integrates smoothly into existing semiconductor manufacturing workflows.
Solution Approach 2:
The use of metal silicide creates a composite material structure that combines the beneficial properties of both metal (electrical conductivity) and silicon (low capacitance, compatibility with semiconductor processes). This composite approach reduces capacitive loading while maintaining ease of manufacture through standard silicidation processes.
Data Source
AI summary
A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.