Metal Silicide Layer Formation via Cap Layer and Inversion
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Solution Overview
Problem
Conventional methods for forming metal silicide layers in semiconductor devices face issues such as boron penetration, depletion effects, and increased risk of short circuits due to contact hole misalignment and size reduction, leading to inferior transistor performance.
Innovation Solution
A method involving the formation of a cap layer that covers the gate structure and does not overlap with the dielectric layer or source/drain regions, allowing for the formation of a metal silicide layer that covers the entire source/drain region before contact hole formation, thereby avoiding material property degradation and ensuring proper ohmic contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact holes are formed after metal silicide layer formation using conventional methods, then the metal silicide layer area is limited by contact hole size and location, but contact hole misalignment and size reduction increase the risk of short circuits and degrade transistor performance
Solution Approach 1:
The metal silicide layer is formed in advance before contact holes are created. This preliminary action ensures that the silicide layer covers the entire source/drain region with optimal area and continuity, independent of subsequent contact hole dimensions or positioning accuracy, thereby eliminating the trade-off between reliability and manufacturing precision
Solution Approach 2:
The conventional sequence is inverted: instead of forming contact holes first then creating metal silicide layers (which limits silicide area to contact hole boundaries), the patent forms metal silicide layers first across the full source/drain region, then creates contact holes through the silicide layer. This inversion allows the silicide layer to achieve maximum coverage without being constrained by contact hole geometry
2Length of moving object
If contact hole size decreases with decreasing critical dimension, then transistor scaling is enabled, but the area of metal silicide layer exposed by contact hole decreases, preventing proper ohmic contact formation
Solution Approach 1:
The metal silicide layer is formed preliminarily before contact hole etching, allowing it to cover the entire source/drain region with sufficient area regardless of the eventual contact hole size. This ensures that when contact holes are formed through the thicker silicide layer, adequate silicide material remains exposed to establish proper ohmic contacts even as critical dimensions scale down
3Reliability
If metal gate is used to replace poly-silicon gate, then depletion effect is reduced and driving force is improved, but boron penetration and material property degradation occur during contact plug formation processes
Solution Approach 1:
The metal silicide layer is formed in advance before contact plug processes, creating a protective silicide cap over the source/drain regions. This preliminary silicide layer acts as a barrier during subsequent contact hole formation and filling processes, preventing boron penetration and protecting the metal gate structure from harmful exposures while maintaining the gate's improved performance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and improves transistor performance by ensuring a consistent and extensive metal silicide layer coverage, independent of contact hole size and location, thereby enhancing electrical performance.
Implementation Method 1
a metal layer is formed to cover the source/drain region, and a self-aligned metal silicide (salicide) process is performed to form a metal silicide layer
Data Source
AI summary
A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed.