Metal Silicide Source Regions in 3D NAND Memory
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in forming efficient metal silicide source regions for vertical NAND strings, which affect the performance and reliability of memory operations.
Innovation Solution
A semiconductor structure and method involving an alternating stack of insulating and conductive layers, where a metal silicide source region is formed by diffusing silicide-forming metal atoms through a vertical semiconductor channel, and a source contact layer is physically exposed and formed on the source region, enabling effective contact and operation of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to form source regions in vertical NAND strings, then the fabrication process requires additional gettering steps, but this increases process complexity and reduces manufacturing efficiency
Solution Approach 1:
The invention extracts and eliminates the gettering step from the conventional fabrication process by directly forming metal silicide source regions through controlled metal deposition and thermal treatment, thereby simplifying the overall manufacturing process while maintaining device performance
Solution Approach 2:
The metal layer is deposited and thermally treated in advance to pre-form the metal silicide source regions before final device assembly, allowing subsequent steps to proceed without additional gettering operations and reducing overall process complexity
2Reliability
If metal silicide source regions are formed by conventional methods, then source contact can be established, but contact resistance and contact area are insufficient for optimal performance
Solution Approach 1:
The invention changes the physical and chemical parameters of the source region by forming metal silicide compounds with specific stoichiometries and crystal structures, thereby optimizing both contact resistance and contact area simultaneously through controlled thermal processing and metal deposition parameters
3Productivity
If the fabrication process includes gettering steps, then source region formation is achieved, but manufacturing time and productivity are reduced
Solution Approach 1:
The invention merges the source region formation process with the metal deposition and thermal treatment steps, eliminating the need for separate gettering operations and thereby reducing total manufacturing time while maintaining source region quality
Solution Approach 2:
The invention skips the conventional gettering step entirely by directly forming functional metal silicide source regions through controlled metal deposition and thermal annealing, thereby accelerating the fabrication process and improving manufacturing productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the contact resistance and area of the source regions, allowing for improved performance and simplifying the fabrication process by eliminating the need for a gettering step, thereby improving the overall reliability and efficiency of the memory device.
Implementation Method 1
forming a source region comprising a metal semiconductor material at a bottom end of the vertical semiconductor channel by vertically diffusing metal atoms of the silicide-forming metal through the vertical semiconductor channel down to the bottom end of the vertical semiconductor channel
Data Source
AI summary
A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.