Metal Source/Drain Features With Thin Epitaxial Interface
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Solution Overview
Problem
Conventional epitaxial source/drain features in multi-gate transistors exhibit less-than-desirable conductivity due to shrinking dimensions, leading to increased contact resistance in semiconductor devices.
Innovation Solution
A method is introduced where a thin epitaxial layer is formed on exposed channel member surfaces, allowing a metal source/drain feature to be filled in the source/drain openings, replacing a substantial portion of the epitaxial source/drain feature to reduce contact resistance, involving the formation of a dummy epitaxial feature, its removal, and subsequent growth of a thin epitaxial layer followed by deposition of a metal silicide layer and source/drain feature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional epitaxial source/drain features are used in multi-gate devices with shrinking dimensions, then device scaling is achieved, but contact resistance increases and conductivity decreases
Solution Approach 1:
The patent combines epitaxial semiconductor material with metal material to form a hybrid source/drain structure. The epitaxial layer provides lattice matching and interface quality, while the metal layer provides high conductivity and low contact resistance, creating a composite structure that overcomes the limitations of conventional single-material source/drain features at scaled dimensions
Solution Approach 2:
The patent changes the material parameter from pure semiconductor to metal-semiconductor composite, and controls the thickness parameter of the epitaxial layer to be thin (allowing sufficient metal penetration) while maintaining interface quality. This parameter optimization enables the metal source/drain feature to effectively reduce contact resistance without compromising device performance
2Reliability
If the epitaxial source/drain feature is replaced with metal source/drain feature, then conductivity is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by first forming the epitaxial source/drain feature, then selectively removing portions to create recesses, and finally filling with metal material. This staged approach simplifies the overall process compared to direct metal deposition, as each step builds on the previous one and uses standard semiconductor fabrication techniques
Solution Approach 2:
The epitaxial source/drain feature serves as an intermediary structure that facilitates the eventual metal filling process. It provides a template and interface layer that enables controlled metal deposition and ensures good electrical contact, acting as a mediator between the channel region and the final metal source/drain feature
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced contact resistance and improved current conduction through the metal source/drain feature, enhancing the conductivity and performance of semiconductor devices.
Implementation Method 1
a thin epitaxial layer is formed on exposed channel member surfaces
Implementation Method 2
deposition of a metal silicide layer
Implementation Method 3
deposition of a metal silicide layer
Data Source
AI summary
A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.