Metal-Containing Source Drain Structures for Nanowire Transistors
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly due to constraints on lithographic processes, which affect the critical dimension and spacing of features in semiconductor fabrication.
Innovation Solution
The implementation of metal-containing source or drain structures with embedded metal species, such as Sn, Al, or C, which are implanted or alloyed into epitaxial semiconductor materials to induce tensile or compressive stress in the channel, enhancing mobility and performance of NMOS and PMOS devices, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to increase device density, then capacity increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control and short channel effect suppression at scaled dimensions while maintaining high device density through vertical stacking of multiple nanowires.
Solution Approach 2:
The patent employs composite material structures including semiconductor-sacrificial material nanowire stacks (e.g., Si/SiGe alternating layers), where the sacrificial material enables selective etching to release individual nanowires. The source/drain regions incorporate stressor materials (e.g., SiC, SiN) combined with semiconductor materials to induce mechanical stress that enhances carrier mobility in the scaled channel region.
2Quantity of substance
If multi-gate and nanowire transistor dimensions are reduced and number increased in a region, then device density increases, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent segments the channel into multiple independent nanowires stacked vertically, with each nanowire surrounded by its own gate. This segmentation allows standard lithographic processes to pattern the planar footprint while the vertical stacking achieves higher effective device density. The segmented approach also simplifies the lithographic requirements compared to attempting to pattern closely spaced planar transistors.
Solution Approach 2:
By moving device stacking into the vertical dimension rather than relying solely on planar lithographic patterning, the patent achieves higher device density without proportionally increasing lithographic complexity. The gate-all-around structure wraps around each nanowire in three dimensions, providing comprehensive control while the vertical arrangement maximizes space utilization without requiring proportionally tighter lithographic features.
3Reliability
If metal species are implanted into epitaxial semiconductor source or drain structures, then mobility and performance improve through induced stress, but manufacturing complexity increases
Solution Approach 1:
The patent modifies the physical and chemical parameters of the source/drain structures by incorporating metal species (e.g., Ti, Ta, W, Mo) during epitaxial growth or through subsequent implantation and annealing processes. These parameter changes induce mechanical stress in the channel region, altering carrier mobility characteristics to enhance device performance while managing the added manufacturing complexity through integrated process flows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves drive performance while reducing power consumption, achieving better performance per Watt by optimizing stress states in the channel region, thereby addressing the limitations of conventional fabrication methods.
Implementation Method 1
The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires
Implementation Method 2
implanted or alloyed into epitaxial semiconductor materials to induce tensile or compressive stress in the channel, enhancing mobility and performance
Data Source
AI summary
Integrated circuit structures having metal-containing source or drain structures, and methods of fabricating integrated circuit structures having metal-containing source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires.