Metal Spacer Patterning for Variable Line Widths
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Solution Overview
Problem
Current metal spacer-based patterning techniques for integrated circuits face challenges in achieving variable line widths and space widths, with Self-aligned Double Patterning (SADP) providing fixed space widths and Litho-Etch-Litho-Etch (LELE) techniques lacking self-alignment, resulting in poor space control as feature pitches shrink.
Innovation Solution
Implementing multiple metal spacer patterning passes with varying widths and materials, where each pass forms metal and dielectric spacers with different widths, allowing for interleaved patterns with fine control over line and space widths, utilizing atomic layer deposition (ALD) for conformal deposition and vertical etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Self-aligned Double Patterning (SADP) is used, then space control is improved, but line width variability is limited to fixed widths
Solution Approach 1:
The patterning process is divided into multiple sequential passes, with each pass creating spacers of different widths. The first pass forms spacers with a first width, the second pass forms spacers with a second width, and subsequent passes add additional width variations. This segmentation allows the final structure to have multiple line widths and spaces, resolving the contradiction between precise space control and line width variability.
Solution Approach 2:
The spacer width is made dynamic by varying the deposition thickness in different passes. Each atomic layer deposition pass deposits material to a controlled thickness that determines the spacer width for that pass. By dynamically adjusting the deposition parameters between passes, the process achieves both precise space control (through conformal deposition) and line width variability (through varying deposition thicknesses).
2Productivity
If feature pitches are shrunk to increase density, then capacity is improved, but space control deteriorates
Solution Approach 1:
The atomic layer deposition process is self-aligning by nature, as it conformally deposits material on all exposed surfaces simultaneously. This self-service mechanism automatically ensures uniform spacer widths without requiring additional alignment steps, maintaining precise space control even as feature pitches are shrunk to increase density.
Solution Approach 2:
The patent replaces mechanical lithographic alignment systems with a chemical vapor deposition-based self-alignment mechanism. Instead of relying on mechanical mask alignment and exposure systems, the process uses conformal atomic layer deposition to automatically define precise spacer positions and widths, maintaining manufacturing precision at smaller pitch dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables integrated circuits with varying line and space widths, providing improved space control and flexibility, suitable for applications requiring different spacings for high and low voltage signals, while maintaining precision below the resolution limit of exposure systems.
Implementation Method 1
utilizing atomic layer deposition (ALD) for conformal deposition
Data Source
AI summary
Metal spacer-based approaches for fabricating conductive lines/interconnects are described. In an example, an integrated circuit structure includes a substrate. A first spacer pattern is on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W1). A second spacer pattern is on the substrate, where the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W2) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers.