Semiconductor Metal Stack Etching for Clean Sidewalls
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices with sintering metal layers face challenges in achieving clean sidewall profiles and avoiding undercuts during patterning, which can lead to reliability issues due to humidity trapping.
Innovation Solution
A two-step etching process is employed, where the upper layers (NiV and Ag) are patterned using wet etching and the lower layers (TiW and Ti) are patterned using dry etching, ensuring a smooth side face profile free of undercuts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching process is used for all metal layers, then the manufacturing process is simpler and faster, but the sidewall profiles are not clean and undercuts occur
Solution Approach 1:
The patent divides the etching process into two distinct segments: wet etching for the upper layers (NiV and Ag) and dry etching for the lower layers (TiW and Ti). This segmentation allows each etching method to be optimized for its specific layer, achieving clean sidewall profiles without undercuts while maintaining manufacturing efficiency
Solution Approach 2:
Different etching methods are applied to different layers based on their specific requirements. The upper layers (NiV and Ag) use wet etching which provides smooth sidewalls, while the lower layers (TiW and Ti) use dry etching which prevents undercuts. This local optimization ensures each layer achieves its ideal profile
2Manufacturing precision
If wet etching is used for all layers, then the sidewalls are smooth, but undercuts occur in the patterned metal stack
Solution Approach 1:
The patent segments the etching process by layer, applying wet etching only to the upper layers (NiV and Ag) where smooth sidewalls are critical, and dry etching to the lower layers (TiW and Ti) where undercut prevention is essential. This eliminates humidity traps while maintaining sidewall quality
Solution Approach 2:
Each layer receives the etching treatment best suited to its properties and position in the stack. The upper layers get wet etching for smoothness, while the lower layers get dry etching to prevent undercuts that would create reliability issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor device with optimal side face profiles, enhancing reliability by preventing humidity traps and reducing manufacturing time while maintaining high electrical and thermal conductivity.
Implementation Method 1
wet etching the Ag layer and the Ni alloy layer
Implementation Method 2
dry etching the Ti layer and the TiW layer
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a TiW layer arranged on the semiconductor substrate a Ti layer arranged on the TiW layer, a Ni alloy layer arranged on the Ti layer, and an Ag layer arranged on the Ni alloy layer, wherein the Ag layer and the Ni alloy layer comprise side faces fabricated by at least one wet etching process, and wherein the Ti layer and the TiW layer comprise side faces fabricated by a dry etching process.


