Semiconductor Metal Stack Etching Without Humidity-Trapping Undercuts

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Solution Overview

Problem

The manufacturing of semiconductor devices with sintering metal layers for high electrical and thermal conductivity requires efficient patterning processes that avoid time-consuming steps and prevent humidity-trapping undercuts, which existing methods fail to address effectively.

Innovation Solution

A method involving the sequential deposition of TiW, Ti, Ni alloy, and Ag layers, where the Ag and Ni alloy layers are patterned using wet etching and the TiW and Ti layers are patterned using dry etching, allowing for optimal side face profiles without undercuts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single etching process is used for all metal layers, then the manufacturing process is simpler and faster, but undercuts are formed in the patterned metal stack which trap humidity and reduce reliability

Engineering Contradiction:

Improveetching process speedVSAvoidpatterned metal stack reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The etching process is segmented into two distinct steps: wet etching for the Ag and Ni alloy layers, and dry etching for the Ti and TiW layers. This segmentation allows each etching method to be optimized for its specific material, preventing undercut formation in the diffusion barrier layer while maintaining manufacturing efficiency.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If wet etching is used for all metal layers, then the process is simpler, but side wall profiles are not clean and undercuts are formed

Engineering Contradiction:

Improveetching process complexityVSAvoidside wall profile quality

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

Different etching methods are applied to different layers based on their specific material properties and required outcomes. Wet etching is used for layers where isotropic etching is acceptable, while dry etching is used for the Ti and TiW layers to achieve clean vertical side wall profiles and prevent undercut formation.

Inventive Principle:

Principle #3Local quality

3Manufacturing precision

If dry etching is used for all metal layers, then clean side wall profiles are achieved, but the processing time increases and costs rise

Engineering Contradiction:

Improveside wall profile cleanlinessVSAvoidtotal etching time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

Dry etching is applied partially, only to the Ti and TiW layers where clean side wall profiles are critical for preventing undercut formation. Wet etching is used for the Ag and Ni alloy layers where it is sufficient and more efficient, thereby reducing total processing time and cost while still achieving the necessary manufacturing precision.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This two-step etching scheme ensures smooth side face profiles and avoids undercuts, enhancing the reliability and efficiency of the semiconductor device fabrication process while maintaining low processing costs.

Implementation Method 1

wet etching the Ag layer and the Ni alloy layer

Methodology Applied

Scientific EffectWet etching:

Implementation Method 2

dry etching the Ti layer and the TiW layer

Methodology Applied

Scientific EffectDry etching:

Data Source

PatentUS12018387B2Method for fabricating a semiconductor device using wet etching and dry etching and semiconductor device

Publication Date: 2024.06.25 INFINEON TECH AUSTRIA AG

AI summary

A method for fabricating a semiconductor device comprises depositing a TiW layer on a semiconductor substrate, depositing a Ti layer on the TiW layer, depositing a Ni alloy layer on the Ti layer, depositing an Ag layer on the Ni alloy layer, at least partially covering the Ag layer with photoresist, wet etching the Ag layer and the Ni alloy layer, and dry etching the Ti layer and the TiW layer.