Metal Pattern Stack Layout for Short-Circuit-Resistant Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in improving the yield rate of electronic devices lies in reducing the possibility of short circuits between metal patterns due to contact, which is exacerbated by the compression of insulating layers, leading to inadequate thickness and increased parasitic capacitance.
Innovation Solution
The electronic device design incorporates a first metal pattern with a thickness ranging from 0.1 μm to 10 μm, a first insulating layer with a thickness that allows a ratio of the second metal pattern's thickness to be greater than 0 and less than or equal to 0.4, thereby maintaining a relatively large insulating layer thickness and reducing the likelihood of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the insulating layer thickness is reduced to accommodate intermediate components, then device integration is improved, but the risk of short circuit between metal patterns increases
Solution Approach 1:
The patent applies parameter changes by establishing a specific thickness ratio relationship between the insulating layer and the second metal pattern (thickness ratio ≤ 0.4). This quantitative parameter control ensures that even when the insulating layer is compressed to accommodate intermediate components, the remaining thickness is sufficient to prevent short circuits while maintaining device integration capability.
2Volume of moving object
If the insulating layer thickness is reduced, then more space is available for intermediate components, but parasitic capacitance increases
Solution Approach 1:
The patent controls parasitic capacitance by establishing a minimum thickness requirement for the insulating layer through the thickness ratio relationship (thickness of second metal pattern / thickness of insulating layer ≤ 0.4). This parameter control allows maximization of space for intermediate components while keeping parasitic capacitance within acceptable limits.
3Productivity
If the thickness ratio of the second metal pattern to the insulating layer is increased, then space utilization is improved, but the insulating layer becomes too thin causing short circuits
Solution Approach 1:
The patent establishes an upper bound for the thickness ratio (≤ 0.4) that simultaneously optimizes space utilization and maintains adequate insulating layer thickness. This parameter specification provides clear manufacturing guidance, ensuring that the insulating layer remains thick enough to prevent short circuits while maximizing space for intermediate components.
Data Source
AI summary
An electronic device including a substrate, a first metal pattern, a first insulating layer, and a second metal pattern is provided. The first metal pattern is disposed on the substrate and has a first thickness. The first insulating layer is disposed on the first metal pattern and has a second thickness. The second metal pattern is disposed on the first insulating layer and has a third thickness. The first thickness ranges from 0.1 μm to 10 μm, and a ratio of the third thickness to the second thickness is greater than 0 and less than or equal to 0.4.