Obscured Metal Stack Tuning for Accurate Parasitic Extraction
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Solution Overview
Problem
Conventional parasitic extraction and circuit verification processes using obscured metal stack definitions in IC manufacture are inaccurate due to slight differences in 3D geometry generation, leading to potential manufacturing defects and lower yields, as they cannot determine parasitic capacitance values with threshold accuracy.
Innovation Solution
The metal stack tuning technology generates sampled metal stack definitions and computes parasitic capacitance value sets to create a lookup table, using curve-fitting to determine tuned values for selected parameters, thereby approximating the actual metal stack definition without exposing confidential parameter values, thus increasing accuracy in circuit analysis and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If obscured metal stack definitions are used to protect confidential manufacturing parameters, then manufacturing security is improved, but parasitic extraction accuracy deteriorates
Solution Approach 1:
The patent introduces an intermediary calibration process that mediates between the obscured metal stack definition (protecting confidentiality) and accurate parasitic extraction (achieving precision). The calibration flow uses sampled definitions and curve-fitting to create a translation layer that maps obscured parameters to accurate electrical characteristics without exposing confidential manufacturing data.
Solution Approach 2:
The patent transforms the problem by changing parameters from direct geometric measurements to electrical characteristic measurements. Instead of using actual geometric parameters from obscured definitions, the system extracts parasitic capacitance values through calibration and uses these electrical parameters directly, bypassing the need to know the obscured geometric details while maintaining extraction accuracy.
2Object-generated harmful factors
If obscured metal stack definitions are used, then manufacturing security is improved, but circuit verification reliability deteriorates
Solution Approach 1:
The calibration flow acts as an intermediary that enables reliable circuit verification using obscured definitions. By pre-calibrating the relationship between obscured geometric parameters and actual electrical characteristics, the system ensures that subsequent extractions on production designs are reliable without requiring access to confidential manufacturing parameters.
Solution Approach 2:
The patent performs preliminary calibration actions before production verification. The calibration flow is executed in advance to establish accurate parameter mappings, so that when circuit verification is performed on production designs, the reliability is ensured by the pre-established calibration data rather than by having access to confidential obscured parameters.
3Object-generated harmful factors
If conventional parasitic extraction is used with obscured definitions, then manufacturing security is maintained, but manufacturing precision deteriorates due to inaccurate parasitic values
Solution Approach 1:
The patent changes the extraction approach from geometric parameter-based extraction to electrical characteristic-based extraction. By using calibrated parasitic capacitance values derived through curve-fitting rather than direct geometric calculations from obscured definitions, the system achieves manufacturing precision without compromising confidentiality.
Solution Approach 2:
The calibration process incorporates feedback mechanisms where extracted parasitic values are compared against expected or measured values, and the model is adjusted accordingly. This feedback loop ensures that even with obscured definitions, the extraction process converges to accurate parasitic capacitance values that meet manufacturing precision requirements.
Data Source
AI summary
A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.