Metal Stacked Bump Structure for Wire Bonding Pressure Resistance
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Solution Overview
Problem
Current chip packages are unable to withstand the positive pressure during wire bonding, leading to potential damage of the internal circuit and increased manufacturing costs due to necessary redesigns.
Innovation Solution
A chip package with metal stacked bumps composed of nickel (Ni) and gold (Au) or nickel (Ni), palladium (Pd), and gold (Au) layers, with a thickness range of 4.5 to 20 μm, enhancing structural strength to endure wire bonding pressures without damaging the internal circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the chip package uses conventional bump structure, then the manufacturing process is simple, but the bump cannot withstand the positive pressure during wire bonding, causing internal circuit damage
Solution Approach 1:
The bump is constructed as a composite structure with a copper core and a nickel outer layer. The copper core provides mechanical strength to withstand wire bonding pressure, while the nickel layer provides corrosion resistance and solderability. This composite material approach resolves the contradiction by achieving high strength without excessive structural complexity.
Solution Approach 2:
The invention transitions from a conventional two-layer bump (Ni/Pd or Ni/Au) to a three-layer composite structure (Cu/Ni/Sn or Cu/Ni). By adding the copper core dimension, the bump gains superior mechanical strength and bearing capacity while maintaining a relatively simple overall structure that is compatible with existing manufacturing processes.
2Strength
If the bump thickness is increased to enhance strength, then the bump can bear wire bonding pressure, but the overall chip package thickness increases
Solution Approach 1:
The copper-nickel composite structure provides high strength-to-thickness ratio. The copper core contributes significantly to mechanical strength, allowing the bump to withstand wire bonding pressure with a thinner overall structure compared to conventional materials, thus reducing the chip package thickness while maintaining required strength.
Solution Approach 2:
By changing the material composition parameters (introducing copper core with specific hardness and the nickel layer thickness), the bump achieves optimal strength properties. The copper core's high strength allows for a thinner bump design that still meets the bearing capacity requirements, thereby controlling the overall chip package thickness.
3Productivity
If the internal circuit is arranged under the die pad, then space utilization is improved, but the positive pressure during wire bonding damages the internal circuit in conventional chip packages
Solution Approach 1:
The copper-nickel composite bump structure provides enhanced mechanical strength and pressure distribution capabilities. This allows the bump to absorb and distribute the wire bonding positive pressure effectively, protecting the internal circuit underneath from damage. Consequently, the internal circuit can be safely arranged under the die pad, improving space utilization and circuit arrangement efficiency.
Solution Approach 2:
The robust copper-nickel composite bump structure acts as a protective cushion before the wire bonding process. Its high strength and pressure distribution properties pre-establish a protective barrier that prevents the positive bonding pressure from reaching and damaging the internal circuit, enabling safe circuit arrangement under the die pad.
Data Source
AI summary
A bump of a chip package with higher bearing capacity in wire bonding is provided. The at least one bump of the chip package is a metal stacked member with a certain thickness. An overall thickness of the bump is 4.5-20 μm. Thereby a structural strength of the bump is improved and thus able to bear positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under at least one die pad or arrange under the die pad of the chip. Thereby increased cost problem caused by internal circuit redesign of the chip can be solved and this helps to reduce cost at manufacturing end.