Retargeting Metal Tip-to-Tip Across Cell Boundaries
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Solution Overview
Problem
In integrated circuit (IC) design, the increasing complexity of feature sizes and interconnect structures leads to accuracy issues in aligning interconnect structures with underlying features, resulting in area waste and unpredictable performance due to the need for larger metal-via enclosures and tip-to-tip spaces, which complicates density scaling and reliability.
Innovation Solution
A processor-based method that detects structure design violations at cell boundaries for metal layers above and below vias, retargeting the via design to generate a corrected semiconductor structure layout, avoiding the insertion of dummy cells and optimizing area usage by adjusting design values for metal layers and vias to ensure proper alignment and contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If larger metal-via enclosures and tip-to-tip spaces are used to improve alignment accuracy, then manufacturing precision is improved, but area waste increases and device complexity increases
Solution Approach 1:
The patent applies local quality by implementing different enclosure rules for different locations: at cell boundaries, the metal enclosure to via is reduced or eliminated, while within cells, standard enclosure rules apply. This localized adjustment resolves the contradiction by maintaining manufacturing precision where needed while reducing area waste at cell boundaries where it is not required for alignment accuracy.
Solution Approach 2:
The patent segments the design space into cell interiors and cell boundaries, applying different enclosure rules to each segment. This segmentation allows the system to maintain precision within cells while eliminating unnecessary enclosure at boundaries, thereby reducing overall area waste without compromising alignment accuracy in critical regions.
2Manufacturing precision
If larger metal-via enclosures and tip-to-tip spaces are used to improve alignment accuracy, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
By applying local quality, the patent simplifies the overall device design by eliminating the need for complex enclosure structures at cell boundaries. The localized reduction of enclosure rules at boundaries while maintaining standard rules within cells reduces design complexity while preserving the necessary alignment accuracy through targeted application of enclosure requirements only where they are critically needed.
3Reliability
If tip-to-tip spacing is increased to improve alignment reliability, then reliability is improved, but area waste increases and density scaling becomes more difficult
Solution Approach 1:
The patent applies local quality by implementing reduced tip-to-tip spacing rules specifically at cell boundaries where full spacing is not required for reliability. Within cell interiors, standard tip-to-tip spacing rules are maintained to ensure alignment reliability. This localized differentiation resolves the contradiction by maintaining reliability where structurally necessary while reducing area waste at boundaries where the reduced spacing does not compromise reliability.
4Reliability
If tip-to-tip spacing is increased to improve alignment reliability, then reliability is improved, but density scaling becomes more difficult
Solution Approach 1:
By implementing local quality with differentiated spacing rules, the patent enables better density scaling by allowing tighter packing of structures at cell boundaries while maintaining reliability within cells. This localized approach to tip-to-tip spacing resolves the contradiction by preserving alignment reliability in critical regions while improving overall density and facilitating scaling across the device.
Data Source
AI summary
A method for structure design including a processor performing error processing of an initial design file layout. The processor detects a structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure. A physical semiconductor structure is generated based on the resulting design file layout of the semiconductor structure.