Semiconductor Metal Track Layout for Single-Patterning Density
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently producing metal tracks with small metal pitches, which require complex and costly double or multiple patterning processes due to resolution limits in photolithography, increasing manufacturing complexity and costs.
Innovation Solution
The approach involves shrinking the length of metal tracks while maintaining or increasing the pitch to accommodate a single patterning process, allowing for higher density and reduced manufacturing complexity by using a single exposure photolithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal pitch is reduced to increase functional density, then area budget is improved, but manufacturing complexity increases due to requirement of double or multi-patterning processes
Solution Approach 1:
The patent changes the optimization dimension from horizontal (reducing metal pitch) to vertical (reducing metal track length). By making metal tracks shorter and arranging them in multiple layers stacked vertically, the design achieves higher functional density without reducing the horizontal pitch, thereby avoiding the need for complex multi-patterning processes while still meeting area requirements
Solution Approach 2:
The patent segments the interconnect structure into multiple metal layers stacked vertically, with each layer containing shorter metal tracks. This segmentation allows the design to achieve high density through vertical stacking rather than horizontal compression, enabling single-patterning manufacturing processes to be used for each layer
2Area of moving object
If metal pitch is reduced to meet area budget, then area efficiency is improved, but process costs increase due to double or multi-patterning requirements
Solution Approach 1:
The patent transitions from two-dimensional horizontal pitch reduction to three-dimensional vertical stacking, achieving area efficiency through increased vertical utilization rather than horizontal compression. This approach maintains larger horizontal pitches that are compatible with cost-effective single-patterning processes
3Device complexity
If metal track length is reduced to enable single patterning, then manufacturing complexity is reduced, but routing capacity must be maintained
Solution Approach 1:
The patent compensates for reduced metal track length by adding vertical dimension through multiple stacked layers. Each layer contains shorter tracks that are easier to manufacture, but the cumulative routing capacity across multiple layers maintains or exceeds the capacity of fewer longer tracks, preserving adaptability while reducing manufacturing complexity
Solution Approach 2:
The patent implements nested routing where multiple metal layers are stacked vertically, with each layer providing additional routing resources. This nested structure allows shorter tracks in each layer to collectively provide sufficient routing capacity through vertical integration
Data Source
AI summary
A structure includes first and second cells next to each other and having first and second cell heights, respectively, along a column direction. Each cell includes at least one semiconductor active region extending lengthwise along a row direction perpendicular to the column direction. The structure further includes an array of metal tracks over the first and second cells. The metal tracks are formed by a photolithography process having a half-pitch resolution Rrow in the row direction. A first pitch of the metal tracks along the row direction is greater than or equal to 2Rrow. At least three rows of the metal tracks are in an area that is directly above the first and second cells and has a height equal to a sum of the first and second cell heights. A row of the metal tracks is disposed across a cell boundary of the first and second cells.