Metal Zero Layer Ge Implantation for Uniform CMP and Low Resistance
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Solution Overview
Problem
The existing manufacturing methods for metal zero layers in semiconductor devices face challenges in controlling the shape and dimension of titanium silicide, leading to increased resistance and defects such as recess and residue due to uneven chemical mechanical polishing, especially at advanced process nodes like 7 nm and 5 nm, where contact resistivity requirements are stringent.
Innovation Solution
A method involving two stages of Ge ion implantation with varying energies and angles to create amorphous silicon layers, followed by metal silicide formation and controlled chemical mechanical polishing using Ge layers as stop layers to ensure uniform polishing and reduce electrochemical reactions, thereby enhancing the dimension and morphology of the metal silicide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If titanium silicide (TiSix) is introduced into the metal zero layer, then contact resistivity is reduced, but the process complexity increases and the shape control of TiSix becomes difficult
Solution Approach 1:
An amorphous silicon layer is introduced as an intermediary between the TiSix metal silicide layer and the underlying structures. This intermediate layer serves multiple functions: it acts as a barrier to prevent excessive TiSix formation, provides a controlled interface for metal deposition, and enables better shape control of the silicide region. The amorphous silicon layer is formed through ion implantation methods, creating a distinct intermediate zone that mediates the interaction between the metal silicide and substrate.
2Reliability
If the volume and contact area of TiSix are reduced, then the metal zero layer resistance increases, but the process control capability deteriorates
Solution Approach 1:
The amorphous silicon layer is formed in advance through ion implantation before the metal silicide deposition step. This preliminary action establishes a pre-defined region with controlled dimensions and properties that will subsequently guide the TiSix formation. The pre-formed amorphous silicon layer acts as a template that limits and shapes the metal silicide growth, ensuring precise dimensional control while maintaining optimal contact area and volume.
3Shape
If chemical mechanical polishing (CMP) is used to planarize the metal zero layer, then surface flatness is improved, but uneven polishing rates in different regions cause defects
Solution Approach 1:
The amorphous silicon layer provides a region-specific polishing stop that creates different polishing characteristics in different areas of the wafer. In pattern-dense regions, the amorphous silicon layer is present and provides a uniform stopping point for CMP, while in pattern-isolation regions, the polishing behavior is naturally different. This local quality approach allows each region to be polished appropriately for its specific pattern density, eliminating the uniform polishing rate assumption that causes defects.
4Shape
If CMP is performed to remove Co outside the trench, then planarization is achieved, but electrochemical reactions during CMP cause recess and residue defects
Solution Approach 1:
The amorphous silicon layer serves as a protective intermediary during the CMP process. It acts as a physical barrier that prevents direct contact between the Co metal and the polishing slurry, thereby eliminating the electrochemical reactions that would otherwise occur. This intermediate layer allows CMP to proceed safely without generating the harmful electrochemical effects that cause recess and residue defects, while still achieving the desired planarization of the metal zero layer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and minimizes defects, ensuring consistent polishing across varying pattern densities and improving the overall resistance and yield of the metal zero layer.
Implementation Method 1
performing first Ge ion implantation, wherein the first Ge ion implantation forms a first Ge layer in the zero interlayer film, and simultaneously the first Ge ion implantation achieves first amorphization on the surface of the source drain epitaxial layer
Implementation Method 2
the first Ge ion implantation achieves first amorphization on the surface of the source drain epitaxial layer at the bottom of the first trench
Data Source
AI summary
The present application discloses a method for manufacturing a metal zero layer, comprising: step 1, etching a zero interlayer film to form a first trench; step 2, performing first Ge ion implantation to form a first Ge layer in the zero interlayer film and achieve first amorphization; step 3, performing second Ge ion implantation to form a second Ge layer in the zero interlayer film and achieve second amorphization, wherein the depth of the second Ge layer is greater than the depth of the first Ge layer, and the second Ge ion implantation is tilt ion implantation; step 4, forming a metal silicide layer on the surface of an amorphous silicon layer in a self-aligned manner; step 5, filling the first trench with a first metal layer; and step 6, performing chemical mechanical polishing to fully remove the first metal layer outside the first trench and achieve planarization.