Metal Zero Layer Layout for Low-Resistance Co MOL Contacts
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Solution Overview
Problem
The miniaturization of semiconductor processes leads to increased complexity and difficulty in manufacturing, particularly at the 7 nm node, where the Co wiring process for contact formation in the middle of line (MOL) limits product yield due to the reactivity of Cobalt (Co), causing oxidation and loss during etching, cleaning, and polishing processes.
Innovation Solution
A method for manufacturing a metal zero layer that involves forming a cut-off dielectric layer in an inter-gate trench, followed by a metal zero layer formed through electroplating, with a barrier and seed layer to prevent Co diffusion, and subsequent oxide layers to ensure planarization and protection, allowing for self-aligned definition of the metal zero layer width without selective etching of the zero interlayer dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Co electroplating is used to form contact in MOL, then metal wiring resistance is reduced, but Co oxidation and loss occur during subsequent processing
Solution Approach 1:
The patent forms a protective capping layer (SiN or SiON) immediately after Co electroplating and before any etching or cleaning operations. This preliminary protective action prevents Co oxidation and loss during subsequent processing steps, resolving the contradiction between achieving low resistance through Co plating and preventing Co degradation during manufacturing.
Solution Approach 2:
The patent introduces a protective capping layer as an intermediary between the Co contact and the subsequent etching/cleaning processes. This intermediary layer acts as a barrier that protects the reactive Co from oxidation and loss while allowing the manufacturing process to continue, thus resolving the contradiction.
2Manufacturing precision
If selective etching of zero interlayer dielectric is performed, then metal zero layer width is defined, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the metal zero layer width definition from the selective etching process of the zero interlayer dielectric. Instead of using selective etching to define the width, the patent forms the metal zero layer with its width predetermined by the trench dimensions and spacer configuration, eliminating the need for subsequent selective etching operations and reducing manufacturing complexity.
Solution Approach 2:
The patent performs preliminary actions to define the metal zero layer width before any dielectric etching operations. The width is predetermined by the trench formation and spacer deposition steps, so when the dielectric is later removed, the metal zero layer width is already established, eliminating the need for selective etching and simplifying the process.
3Reliability
If Co is used in MOL, then electrical property is improved, but process yield decreases due to Co reactivity
Solution Approach 1:
The patent applies a protective capping layer immediately after Co electroplating as a preliminary protective measure. This prevents Co oxidation and loss during subsequent etching and cleaning operations, thereby maintaining process yield while preserving the electrical properties benefits of using Co in the middle of line.
Solution Approach 2:
The protective capping layer serves as an intermediary that shields the reactive Co from harmful interactions during manufacturing processes. This intermediary protection enables the use of Co for its superior electrical properties while preventing the yield-decreasing oxidation and loss that would otherwise occur during subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the contact area between the metal zero layer and source/drain regions, reduces contact resistance, prevents damage to embedded epitaxial layers, minimizes the risk of short circuits, and reduces thermal load on the HKMG process, thereby improving device performance and yield while simplifying the manufacturing process.
Implementation Method 1
forming a barrier and seed layer (B/S) on the bottom and sidewall of an oxide trench
Implementation Method 2
filling the trench with Co by means of electroplating
Implementation Method 3
after being polished by chemical mechanical polishing (CMP)
Implementation Method 4
Co needs to be quickly covered with a SiN protective layer so as to reduce oxidation and loss of Co
Data Source
AI summary
The application discloses a method for manufacturing a metal zero layer, comprising: step 1, providing a semiconductor substrate that undergoes a source and drain formation process of FEOL, wherein an inter-gate trench is formed in an area between dummy gate structures; step 2, forming a cut-off layer of metal zero layer in a selected area of the inter-gate trench; step 3, forming a metal zero layer in the inter-gate trench outside the cut-off layer of metal zero layer, and etching back the metal zero layer; step 4, forming a second oxide layer, the second oxide layer fully filling the inter-gate trench on the top surface of the metal zero layer, performing a planarization process to make the top surface of the second oxide layer level with the top surface of the dummy gate structure; and step 5, removing the dummy gate structure, and forming a second gate structure.