Metal Zero Power Stub Layout for Smaller Standard Cells
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Solution Overview
Problem
The placement of power and ground connections in standard cells for semiconductor chips leads to increased on-die area, which is inefficient and limits the design cycle and time to market due to capacitive coupling, electromigration, leakage currents, and processing yield issues.
Innovation Solution
The use of metal zero power and ground stubs for power and ground connections, eliminating vias to upper metal layers, and aligning these connections to the cell boundary edge for abutment with neighboring cells, allowing for efficient layout without expanding the cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power and ground connections use long wires with multiple metal layers and vias, then reliable power delivery is achieved, but cell area increases significantly
Solution Approach 1:
The patent transitions power and ground connections from upper metal layers (requiring vias) to metal zero layer, utilizing the substrate plane dimension. This dimensional change eliminates via requirements and reduces connection path length, thereby maintaining reliability while significantly reducing cell area.
Solution Approach 2:
The patent extracts the via components from the power and ground connection path by routing all connections through metal zero layer only. This removal of intermediate connection elements (vias) simplifies the structure, reduces area, and eliminates via-related reliability issues while maintaining electrical connectivity.
2Ease of manufacture
If standard cell layouts are expanded to accommodate power and ground connections, then complete power delivery network is achieved, but on-die area consumption increases
Solution Approach 1:
The patent merges the power and ground connection routing into the metal zero layer, combining multiple functions (power delivery, ground reference, signal routing) into a single layer. This consolidation eliminates the need for separate via structures and upper layer routing, achieving complete power networks without expanding cell area.
Solution Approach 2:
Instead of the conventional approach of routing power and ground through upper metal layers with vias, the patent inverts the routing strategy by using metal zero layer as the primary routing plane. This inversion eliminates via requirements and reduces area consumption while maintaining complete power network functionality.
3Manufacturing precision
If manual cell layout creation is performed to satisfy multiple design rules, then design quality is improved, but design cycle time increases
Solution Approach 1:
The patent changes the routing parameter from multi-layer with vias to single-layer metal zero routing. This parameter change automatically satisfies multiple design rules (via clearance, layer stacking, etc.) and eliminates manual layout adjustments, thereby maintaining design quality while reducing design cycle time.
Data Source
AI summary
A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to power and ground posts in metal zero of a neighboring cell by abutment. The place-and-route tool doesn't need to perform a further routing step after placing the cells. For other variations, the power and ground posts are not routed to the boundary edge and the place-and-route tool routes power and ground connections in metal zero between the standard cell and the neighbor cell.