3D Metalization Stack Resistor for Low-Capacitance High Resistance
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Solution Overview
Problem
Existing resistor technologies in semiconductor devices require significant area and introduce high parasitic capacitance, making them unsuitable for high-density and high-speed signal monitoring applications.
Innovation Solution
Implementing resistors using multiple metalization layer interconnect line segments with serpentine layouts and trench contacts, avoiding channel connections to the substrate, to achieve medium or high resistance with low parasitic capacitance and reduced area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If thin-film resistors are used to achieve medium and high resistance values, then the required resistance is obtained, but the area occupied increases significantly
Solution Approach 1:
The patent transitions from planar thin-film resistor structures to three-dimensional metal interconnect stack structures utilizing multiple metallization layers (M0, M1, M2, etc.). By stacking conductive elements vertically and connecting them through vias, the design achieves high resistance values through the cumulative effect of multiple layer segments rather than relying on large-area single-layer films.
Solution Approach 2:
The resistor is divided into multiple discrete metal interconnect line segments distributed across different metallization layers. Each segment contributes a portion of the total resistance, and the segments are connected vertically through vias. This segmentation allows the resistance to be distributed throughout the three-dimensional structure, reducing the area footprint compared to concentrated thin-film designs.
2Measurement precision
If thin-film resistors are used to achieve medium and high resistance values, then the required resistance is obtained, but parasitic capacitance increases
Solution Approach 1:
By moving from two-dimensional thin-film structures to three-dimensional metal interconnect stacks, the design reduces parasitic capacitance. The vertical stacking and distributed segmentation across multiple layers minimize the overlap area between conductive elements and adjacent signal lines, thereby reducing capacitive coupling effects that are prevalent in planar configurations.
Solution Approach 2:
Segmenting the resistor into multiple small metal interconnect pieces across different layers reduces the continuous conductive area that would otherwise generate parasitic capacitance. The vias connecting these segments create discrete connection points rather than large-area contacts, minimizing capacitive coupling to substrate and adjacent structures.
3Reliability
If conventional resistor designs are used, then resistance functionality is achieved, but the area footprint prevents high-density integration
Solution Approach 1:
The metal interconnect structures originally designed for signal routing and power delivery are repurposed to provide resistance functionality. The same metallization layers (M0, M1, M2, etc.) that serve interconnect purposes are configured with specific geometries and series connections to achieve desired resistance values, eliminating the need for dedicated resistor structures and enabling high-density integration.
Solution Approach 2:
The design utilizes the vertical dimension by stacking metal interconnect layers to achieve resistance values without increasing lateral footprint. The three-dimensional arrangement of metal segments and vias allows high resistance values to be compacted into a small area, enabling dense integration of resistors with other circuit elements on the same chip.
Data Source
AI summary
Some examples include a resistor structure formed from interconnect line segments in multiple metalization layers of an integrated circuit device. The line segments include contacts from at least one dummy transistor.