Self-Aligned Metalized Laminate for Dense Interconnection Wiring
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Solution Overview
Problem
The miniaturization of semiconductor devices faces challenges in forming high-density interconnect structures due to the need for fine metal wires and small line spacing, leading to misaligned conductive vias and increased manufacturing costs.
Innovation Solution
A method involving the formation of interconnection wire and via layers on a substrate using photolithography, where interconnection wires and conductive vias are integrated and self-aligned by patterning a metal layer and thinning specific parts to form both structures simultaneously, eliminating the need for filling processes and diffusion barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If extremely fine metal wires are used to achieve high-density interconnect structures, then the integration density is improved, but the manufacturing precision deteriorates due to misaligned conductive vias and difficulty in filling contact holes
Solution Approach 1:
The patent merges the formation of interconnection wires and conductive vias into a single integrated structure. By forming both features from the same metal layer using the same patterning process, the invention eliminates the alignment issues between separate wire and via formation steps, while achieving high integration density through the unified structure
Solution Approach 2:
The metal layer serves multiple functions simultaneously - it forms both the interconnection wires and the conductive vias. This multi-functional approach allows a single patterning and thinning process to create both feature types, improving manufacturing precision while maintaining high integration density
2Quantity of substance
If extremely fine metal wires with small grain size are used, then the integration density is improved, but the resistance increases due to excessive barrier thickness
Solution Approach 1:
The invention changes the physical parameters of the metal structure by creating an integrated wire-via geometry. The continuous metal structure eliminates traditional barrier layer interruptions, reducing effective barrier thickness and electrical resistance while maintaining the fine dimensions needed for high integration density
3Ease of manufacture
If traditional separate formation processes are used for interconnection wires and conductive vias, then the manufacturing flexibility is maintained, but the device complexity increases and manufacturing cost increases
Solution Approach 1:
The patent combines multiple formation steps into a single integrated process. By forming both interconnection wires and conductive vias from the same metal layer in one patterning and thinning sequence, the invention reduces process complexity and manufacturing steps while maintaining ease of manufacture through a unified approach
Data Source
AI summary
A metallic stack and a preparing method therefor, and an electronic device including the metallic stack. The metallic stack includes at least one interconnection wire layer and at least one via layer alternately arranged on a substrate. At least one pair of interconnection wire layer and via layer in the metallic stack includes interconnection wires in the interconnection wire layer and conductive vias in the via layer, wherein the interconnection wire layer is closer to the substrate than the via layer. At least a part of the interconnection wires is integrated with the conductive vias on the at least a part of the interconnection wires.