Metallic eFuse Link Over III-V Semiconductors for Predictable Resistance
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Solution Overview
Problem
Existing electrically programmable fuses (efuses) in III-V semiconductor materials, such as gallium nitride high electron mobility transistors (GaN HEMTs), face integration challenges due to unpredictable resistance in triple well structures and require a larger surface area, posing reliability concerns.
Innovation Solution
A structure incorporating a metallic layer with lower resistivity than the uppermost semiconductor layer, featuring a pair of gate conductors that define an efuse link, allowing for predictable and reliable operation by destroying the efuse with a minimum current, integrated with III-V semiconductor substrates like GaN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If triple well structures are used for efuses in III-V semiconductor materials, then the efuse can be integrated with GaN HEMTs, but the resistance becomes unpredictable and reliability decreases
Solution Approach 1:
The patent changes the material parameter from semiconductor (AlGaN/GaN) to metallic (titanium nitride, TiN). This material substitution fundamentally alters the electrical characteristics, providing predictable and stable resistance values that are independent of the underlying III-V semiconductor structure, thereby resolving the unpredictability issue while maintaining integration capability
Solution Approach 2:
The patent creates a composite structure by placing a metallic TiN layer over the III-V semiconductor layers. This composite approach combines the advantages of both materials: the TiN provides predictable resistive behavior for the efuse function, while the underlying AlGaN/GaN layers maintain the high electron mobility transistor performance, achieving both reliability and adaptability
2Adaptability or versatility
If traditional efuse structures are used in III-V semiconductors, then integration is achieved, but the surface area requirement increases
Solution Approach 1:
By changing from semiconductor-based efuse to metallic TiN-based efuse, the resistivity parameter is dramatically reduced. This allows the efuse link to be made much smaller in cross-sectional area while maintaining the same resistance value, thereby reducing the overall surface area footprint of the efuse structure
Solution Approach 2:
The patent adopts the efuse link concept from silicon technology and replicates it using TiN in III-V semiconductors. This copying of the metallic link approach from established processes enables compact efuse implementation without requiring large surface areas, as the TiN layer can be formed using standard thin-film deposition techniques
3Reliability
If metallic layer with lower resistivity is used, then efuse operation becomes predictable and reliable, but integration complexity may increase
Solution Approach 1:
The TiN layer serves multiple functions simultaneously: it provides the resistive element for the efuse link, acts as a conductive interconnect layer, and can serve as part of the gate structure. This multi-functionality reduces the need for separate dedicated layers, thereby simplifying the overall device structure despite the material change
Solution Approach 2:
The patent merges the efuse link function with the gate conductor structure. The TiN layer that forms the efuse link is the same material and layer that serves as the gate electrode, eliminating the need for separate efuse and gate structures. This merging reduces device complexity while maintaining predictable resistance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact and reliable efuse structure that integrates seamlessly with III-V semiconductor devices, ensuring predictable resistance and reducing the surface area requirement, enhancing device reliability and efficiency.
Implementation Method 1
a metallic layer on the plurality of crystalline semiconductor layers, wherein the metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers
Implementation Method 2
An electrically programmable fuse (efuse) is an electrical connection between two nodes that is configured to be destroyed in response to an electrical current
Implementation Method 3
gradual electromigration degradation
Data Source
AI summary
Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.