Metallic Compound Gate Stack for Reduced Leakage Current
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving dual work functions for gate electrodes near the valence and conduction band edges of silicon, while maintaining high electrical conductivity, which limits their performance, especially for high-k gate dielectric materials.
Innovation Solution
A semiconductor structure with a gate stack comprising a high-k gate dielectric layer and a metallic compound layer with a work function of 4.0 eV or less, including materials like tantalum carbide and hafnium-silicon alloys, is used to optimize the performance of n-type field effect transistors, and a p-type work function material layer is used to achieve the required threshold voltages for p-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional polysilicon gate electrodes are used, then manufacturing is simpler, but gate leakage current increases and performance deteriorates
Solution Approach 1:
The patent employs composite gate electrode structures combining metal layers (such as tungsten, titanium nitride) with high-k dielectric materials. This composite approach reduces gate leakage current while maintaining electrical conductivity, resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent changes the work function parameters of gate electrodes by using different metal materials and doping concentrations. By adjusting these parameters, the gate leakage current is reduced while maintaining the necessary electrical properties, thus improving reliability without excessive complexity.
2Manufacturing precision
If dual work function gate materials are employed, then threshold voltage optimization improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies different work function materials locally to different transistor types (nMOS and pMOS) within the same semiconductor device. This local differentiation enables precise threshold voltage optimization for each transistor type while using a systematic approach that manages manufacturing complexity.
Solution Approach 2:
The gate electrode structure is segmented into multiple functional layers with different materials and properties. This segmentation allows independent optimization of threshold voltages for nMOS and pMOS transistors while maintaining a structured manufacturing process.
3Reliability
If high-k gate dielectric materials are used, then gate leakage current reduces, but achieving required work functions becomes more difficult
Solution Approach 1:
The patent combines high-k dielectric materials with metal gate materials to form composite structures. This combination achieves the desired work functions while utilizing the low leakage properties of high-k dielectrics, balancing ease of manufacture with performance requirements.
Solution Approach 2:
The patent uses intermediate metal layers as mediators between the high-k dielectric and the semiconductor channel. These intermediate layers help achieve the required work functions while maintaining the benefits of high-k dielectric materials, simplifying the manufacturing process.
Data Source
AI summary
Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.


