Metallic Interconnects with Wrap-Around Capping Layers
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Solution Overview
Problem
Conventional BEOL process technologies using chemical-mechanical planarizing (CMP) result in poor quality copper interconnects due to non-uniform surface topography, over polishing of ILD layers, and CMP-induced defects, leading to increased electrical resistivity and reliability issues in semiconductor fabrication.
Innovation Solution
A liner planarization-free process flow that includes forming a sacrificial layer to protect the ILD layer, using wet etching instead of CMP to remove overburden metallic liner material, and applying a heat treatment to convert copper microstructure to larger grains, thereby maintaining high-quality copper in upper regions and preventing CMP-induced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to remove overburden barrier diffusion liner material, then complete removal of overburden material is achieved, but upper portion of copper metallization is removed resulting in increased resistance
Solution Approach 1:
A sacrificial layer is formed over the ILD layer before forming the copper interconnect structures. This sacrificial layer serves as a protective barrier during subsequent processing steps, preventing removal of the ILD layer and protecting the copper metallization from over-polishing. The sacrificial layer is selectively removed after it has served its protective function, allowing complete removal of overburden barrier diffusion liner material without damaging the copper structure.
2Manufacturing precision
If CMP process is used to remove overburden barrier diffusion liner material, then uniform surface is achieved, but CMP induced defects are created at the interface providing conductive paths
Solution Approach 1:
The sacrificial layer acts as an intermediary protective layer between the ILD layer and the CMP process. It absorbs the mechanical stress and chemical action of the CMP process, preventing direct contact between the CMP slurry and the ILD layer surface. This eliminates CMP-induced defects such as carbon depletion and surface damage that would otherwise create conductive paths and lead to time-dependent dielectric breakdown.
3Manufacturing precision
If over polishing of ILD layer is performed to ensure complete removal of overburden material, then electrical shorts are avoided, but upper portion of copper metallization is removed
Solution Approach 1:
The sacrificial layer is formed in advance to provide a stopping point for the CMP process. By designing the sacrificial layer with appropriate thickness and etch selectivity, the CMP process can be controlled to remove all overburden barrier diffusion liner material while stopping precisely at the sacrificial layer interface, preventing removal of the copper metallization layer beneath.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of low-resistance, high-reliability BEOL interconnect structures by avoiding over polishing and CMP-induced defects, maintaining large metallic grains in upper regions of the metallization, and enhancing the reliability of copper interconnects.
Implementation Method 1
performing a chemical-mechanical planarizing process to remove an overburden portion of the layer of metallic material down to an overburden portion of the liner layer
Implementation Method 2
performing a first wet etch process to remove the overburden portion of the liner layer selectively to the sacrificial layer and the metallic interconnect structure
Implementation Method 3
applying a heat treatment to convert copper microstructure to larger grains
Implementation Method 4
performing a heat treatment to convert a first microstructure of at least a portion of the copper interconnect structure to a second microstructure comprising an average grain size which is greater than an average grain size of the first microstructure
Data Source
AI summary
Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.