Metallic Resistor Structure Single Etching Process
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Solution Overview
Problem
Existing methods for forming metallic resistors in semiconductor devices require multiple independent etching processes, increasing manufacturing costs and process steps, and suffer from poor electrical performance due to proximity to the silicon substrate.
Innovation Solution
A method involving a substrate with metallic interconnection structures and dielectric layers, where a metallic resistor is formed through a single etching process using a patterned mask layer, reducing processing steps and cost, and minimizing stray capacitance by positioning the resistor away from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent photoetching or etching processes are used to form metallic resistors, then the metallic resistor can be formed with good electrical performance, but the process complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of metallic resistors and metallic interconnection structures into a single integrated etching process. The patterned mask layer simultaneously defines both the resistor regions and the interconnection hole regions, eliminating the need for separate photoetching steps and reducing process complexity while maintaining electrical performance
2Reliability
If independent photoetching or etching processes are used to form metallic resistors, then the metallic resistor can be formed with good electrical performance, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple manufacturing steps into one etching process, reducing the number of process steps required. This integration directly lowers manufacturing cost by eliminating redundant process equipment usage, material consumption, and processing time while still achieving the desired electrical performance of metallic resistors
3Ease of manufacture
If poly resistor is used in semiconductor devices, then the manufacturing process is simple, but the voltage coefficient and parasitic capacitance performance are poor
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to metallic material for the resistor formation. This material substitution fundamentally improves the electrical performance parameters (voltage coefficient and parasitic capacitance) while the integrated process design maintains manufacturing simplicity by combining the metallic resistor formation with interconnection structure fabrication
4Ease of manufacture
If metallic resistor is positioned close to silicon substrate, then the manufacturing process is simplified, but the parasitic capacitance increases
Solution Approach 1:
The patent utilizes the vertical dimension by positioning the metallic resistor in upper interconnection layers rather than close to the silicon substrate. This spatial arrangement in the vertical dimension reduces parasitic capacitance while the integrated etching process maintains manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and processing steps by forming both capacitors and resistors in a single etching process, while minimizing stray capacitance and enhancing electrical performance by isolating the metallic resistor from the substrate.
Implementation Method 1
etching, by using the patterned mask layer as a mask, until the substrate is exposed
Data Source
AI summary
A metal resistor structure and a method for forming the same are provided. The method includes: providing a substrate including a first and a second metallic plugs disposed in a first and a second regions respectively; forming a first metallic layer on the substrate; forming an insulating material layer on the first metallic layer; patterning the insulating material layer to form a first and a second insulating layer above the first and the second regions respectively; forming a second metallic layer overlaying exposed part of the first metallic layer, the first insulating layer, and the second insulating layer; forming a patterned mask layer on the second metallic layer; and etching, by using the patterned mask layer as a mask, until the substrate is exposed. Accordingly, a capacitor and a metallic resistor are formed on a set of steps, thus processing steps for forming the metallic resistor can be reduced.