Metallic Source/Drain Stack Layout for Lower Contact Resistance
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Solution Overview
Problem
Integrated circuit devices face challenges in reducing parasitic capacitance and contact resistance, which hinder operation speed and integration density, particularly in the middle-of-line (MOL) and back-end-of-line (BEOL) portions of device fabrication.
Innovation Solution
The implementation of a metallic source/drain region structure with a metal interconnector and a back side power distribution network (BSPDN) simplifies the MOL and BEOL fabrication processes, reducing contact resistance and enhancing integration density by using metal layers for source/drain regions and interconnectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor source/drain regions are used, then device structure is conventional and fabrication is standard, but contact resistance is high and operation speed is limited
Solution Approach 1:
The patent changes the material parameter of the source/drain regions from semiconductor to metal, fundamentally altering the electrical properties. This material substitution reduces contact resistance and improves conductivity, directly addressing the reliability issue while accepting increased structural complexity
Solution Approach 2:
The patent employs composite material structures where metal layers are integrated with semiconductor channels and insulating layers. The metallic source/drain regions are formed as composite structures with specific layer configurations (e.g., tungsten, cobalt, or copper layers) that combine the advantages of metal conductivity with semiconductor device architecture
2Speed
If metal layers are used for source/drain regions, then contact resistance is reduced and operation speed improves, but fabrication process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the metallic source/drain regions before complete device assembly and testing. The metal layers are deposited and patterned in advance, allowing for optimization of the fabrication sequence and reducing the complexity of subsequent processing steps
Solution Approach 2:
The patent transitions from planar semiconductor source/drain structures to three-dimensional metallic structures with multiple layers and vertical stacking. This dimensional change enables improved electrical performance while the fabrication complexity is managed through advanced deposition and etching techniques applied in the vertical dimension
3Productivity
If conventional fabrication processes are used, then manufacturing is simpler, but integration density is limited and performance is reduced
Solution Approach 1:
The patent utilizes vertical stacking of metallic source/drain regions with insulating layers and gate structures in the third dimension. This three-dimensional architecture dramatically increases integration density by stacking multiple device layers vertically, allowing more transistors per unit area while managing fabrication complexity through conformal deposition and selective etching processes
Solution Approach 2:
The patent implements nested structures where insulating layers are positioned between and around metallic source/drain regions, and gate structures are nested within the vertical stack. This nested arrangement optimizes space utilization and achieves high integration density while the fabrication process integrates multiple material depositions and patterning steps
Data Source
AI summary
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a substrate and a transistor stack on the substrate. The transistor stack comprises a first transistor and a second transistor stacked in a first direction. The first transistor comprises first and second source/drain regions and a first channel region between the first and second source/drain regions, and the first source/drain region comprises a first metal layer. The second transistor comprises third and fourth source/drain regions and a second channel region between the third and fourth source/drain regions, and the first and third source/drain regions overlap each other in the first direction. The transistor stack further comprises a metal interconnector contacting the third source/drain region and the first metal layer of the first source/drain region material.