Metallic Source Drain Transistor Silicide Sidewall Isolation
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Solution Overview
Problem
Existing methods for manufacturing MOS transistors with metallic source and drain require selective removal of metals to prevent short circuits, limiting the choice of metals and being sensitive to silicon layer thickness, which complicates the process and can lead to inconsistent transistor performance.
Innovation Solution
A method involving the formation of silicide on the sidewalls of the transistor channel, followed by deposition of a second metallic layer to form the source and drain, with chemical mechanical polishing to prevent short circuits, allowing for the use of metals that cannot be selectively etched, thereby reducing access resistance and increasing current output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective removal of metal is performed to prevent short circuits, then short circuit prevention is achieved, but the choice of metals is limited and process complexity increases
Solution Approach 1:
The patent extracts the problematic selective etching step entirely from the process. Instead of removing metal selectively, the method uses a planarization layer (CMP) to remove excess metal uniformly across the substrate, eliminating the need for selective metal removal while preventing short circuits between transistors and other structures
Solution Approach 2:
The patent makes the metal layer universally applicable by removing the selective etching constraint. The CMP planarization step serves multiple functions: it removes excess metal uniformly, prevents short circuits between adjacent transistors, and creates a flat surface for subsequent processing, allowing use of metals like tungsten that would otherwise be incompatible with selective etching
2Manufacturing precision
If silicide penetration into active layer is controlled, then transistor characteristics consistency is improved, but process sensitivity to initial silicon thickness increases
Solution Approach 1:
The patent performs preliminary planarization of the substrate surface before depositing the metal layer. By using CMP to create a flat surface and uniform thickness regions before metal deposition, the process eliminates sensitivity to initial silicon thickness variations, ensuring consistent silicide formation and transistor characteristics across the substrate
3Reliability
If metallic layers are etched before CMP step, then source/drain short circuit is eliminated, but metallic spacers form around gates maintaining short circuit
Solution Approach 1:
The patent inverts the traditional sequence by performing CMP planarization before any metal etching steps. This ensures that excess metal is removed uniformly across the substrate first, preventing metallic spacer formation around gates. Subsequent selective etching then removes metal only where needed without creating harmful spacers, as the surface is already planarized
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the transistor manufacturing process by eliminating the need for selective metal etching, allowing for the use of low-resistive metals and improving current output, while being compatible with various channel materials and transistor architectures, including single and double gate transistors.
Implementation Method 1
annealing to form portions of a metal/semiconductor alloy called a silicide when the semiconductor is made of silicon
Implementation Method 2
form portions of a metal/semiconductor alloy called a silicide
Implementation Method 3
Chemical Mechanical Polishing (CMP) is done to eliminate the internal short circuit
Data Source
AI summary
A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field effect transistor, a gate located on the channel; forming at least one dielectric portion completely covering said structure and zones of the substrate corresponding to locations of a source and a drain of the field effect transistor; making two holes in the dielectric portion on each side of said structure, such that the locations of the source and the drain form bottom walls of the two holes and sides of the channel are exposed; depositing a first metallic layer on at least the bottom walls of the two holes, at least covering said sides of the channel; and depositing a second metallic layer on the first metallic layer-to form the source and the drain of the field effect transistor.