Metallic Source and Drain Regions in Tri-Gate Transistors
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Solution Overview
Problem
The fabrication of tri-gate transistors on bulk silicon substrates faces challenges in aligning the metal gate electrode with the source and drain extension tips, leading to issues like punch-through and unwanted gate capacitance, and existing techniques have not adequately reduced external resistance (Rext) in semiconductor devices.
Innovation Solution
The implementation of metallic source and drain regions with conformal semiconducting out-diffusion regions, which are self-aligned to the gate electrode stack, replacing conventional doped semiconductor regions and using sacrificial source/drain/tip regions formed through undercut etch and silicon germanium epitaxy to reduce series resistance and parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doped semiconductor source and drain regions are used, then the fabrication process is simpler, but the external resistance (Rext) is too high
Solution Approach 1:
The patent changes the material parameter of the source and drain regions from doped semiconductor to metal, which has fundamentally different electrical properties including much lower resistivity. This parameter change directly reduces external resistance while the self-aligned fabrication process manages the complexity increase.
Solution Approach 2:
The patent employs a composite structure combining metal source/drain regions with semiconductor channel regions, and further combines these with dielectric materials for isolation. This composite approach allows optimization of each region's properties - metal for low resistance, semiconductor for active device function, and dielectric for isolation - thereby reducing overall external resistance while maintaining manufacturability.
2Reliability
If the metal gate electrode is deeper than the source and drain extension tips, then gate control is improved, but unwanted gate capacitance parasitics increase
Solution Approach 1:
The patent implements self-aligned fabrication where the metal gate electrode and source/drain regions automatically achieve proper relative positioning through the fabrication process itself, without requiring additional alignment steps. This self-service mechanism ensures the gate depth is optimally positioned to balance gate control improvement while minimizing parasitic capacitance generation.
Solution Approach 2:
The patent replaces conventional doped semiconductor source/drain regions with metal regions, which have fundamentally different electrical properties. This substitution changes the electrical characteristics at the gate-source/drain interface, thereby reducing unwanted gate capacitance parasitics while maintaining effective gate control.
3Manufacturing precision
If the source and drain extension tips are deeper than the metal gate electrode, then alignment tolerance is increased, but punch-through occurs
Solution Approach 1:
The self-aligned fabrication process automatically positions the metal gate electrode and source/drain regions at the correct relative depths through the fabrication sequence itself. This eliminates the need for separate alignment steps and ensures that the gate depth is always appropriate to prevent punch-through, while the metal source/drain regions provide sufficient alignment tolerance.
Solution Approach 2:
By changing the source/drain regions from doped semiconductor to metal, the patent alters the electrical and physical properties of these regions. The metal regions have different etch rates and deposition characteristics, which are exploited in the self-aligned process to achieve proper depth alignment that prevents punch-through while maintaining manufacturing precision.
4Power
If conventional fabrication processes are used, then process simplicity is maintained, but drive current is insufficient
Solution Approach 1:
The patent fundamentally changes the material parameter of the source and drain regions from doped semiconductor to metal, which has much lower resistivity. This parameter change directly increases drive current by reducing the resistance in the source and drain regions, enabling better current flow through the device.
Solution Approach 2:
The patent applies different material qualities to different regions of the device - metal for source/drain regions to minimize resistance and maximize current, semiconductor for the channel to maintain device functionality, and dielectric for isolation. This local quality differentiation optimizes drive current while managing fabrication complexity through specialized processes for each region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves drive current by decreasing series resistance and reduces parasitic resistance in tri-gate and fin-FET devices, enabling better gate control and reducing unwanted capacitance, thus enhancing the performance of semiconductor devices.
Implementation Method 1
sacrificial source/drain/tip regions formed through undercut etch
Implementation Method 2
silicon germanium epitaxy
Implementation Method 3
conformal semiconducting out-diffusion regions
Data Source
AI summary
Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.