Metallization Layer Layout Using Resistive Metal to Cut Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor die fabrication processes result in high parasitic capacitance due to the use of resistive materials in dielectric layers, which degrades the dielectric constant and increases capacitance, affecting signal integrity and performance.
Innovation Solution
Incorporating a resistive metal into the metal layer of the metallization layer, adjacent to the dielectric layer, to act as a resistor element, thereby reducing parasitic capacitance and maintaining the dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If resistive material is deposited in the dielectric layer to form a resistor, then the resistor can be formed with good etch selectivity, but parasitic capacitance increases due to dielectric layer degradation
Solution Approach 1:
The resistive material is extracted from the dielectric layer and relocated to the metal layer. This separation removes the harmful interaction between resistive material and dielectric material, eliminating the source of parasitic capacitance while preserving the resistor formation capability in the metal layer where it does not degrade the dielectric constant.
Solution Approach 2:
The resistor is formed in a different dimensional location - moving from the horizontal plane of the dielectric layer to the vertical metal layer above/below it. This spatial repositioning allows the resistive material to perform its resistance function without being embedded in or degrading the dielectric layer, thus reducing parasitic capacitance.
2Ease of manufacture
If conventional fabrication processes are used with resistive material in dielectric layer, then manufacturing is simplified, but dielectric constant degrades increasing capacitance
Solution Approach 1:
The resistive material is extracted from the dielectric layer and placed in the metal layer, eliminating the degradation of dielectric constant while maintaining a relatively simple fabrication process using standard sputtering and etching techniques.
Solution Approach 2:
The metal layer becomes a composite structure containing both conductive metal (for interconnects) and resistive material (for resistors). This composite approach allows both functions to coexist in the same layer without the harmful interactions that occur when resistive material is mixed with dielectric material.
Data Source
AI summary
Aspects disclosed in the detailed description include a semiconductor die having a metallization layer including a metal layer and a resistive metal in the metal layer to decrease parasitic capacitance in the metallization layer. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, the semiconductor die is provided comprising a metallization layer wherein the metallization layer comprises a dielectric layer having a via and a metal layer adjacent to the dielectric layer. The metal layer comprises a resistive metal coupled to the via. The resistive metal acts as a resistor element in an electronic circuit. Utilizing resistive metal in the metal layer advantageously decreases parasitic capacitance in the metallization layer, and, more specifically, in the dielectric layer resulting from conventional processes which deploy resistive material in the dielectric layer.