Metallization Pitch Realignment for Dense 3D Die Assemblies
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Solution Overview
Problem
Existing integrated circuit designs face inefficiencies in utilizing available silicon area due to limitations imposed by bond pad via and through silicon via pitch, leading to underutilization of device active area in 3D stacked integrated circuits.
Innovation Solution
Implementing a metallization structure that extends metal lines laterally to realign logic elements within the device region, allowing them to be arrayed at a tighter pitch than the bond pad via or through silicon via pitch, thereby optimizing area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If logic elements are arrayed at the same pitch as bond pad vias or through silicon vias, then alignment and bonding are simplified, but silicon area utilization is reduced
Solution Approach 1:
The patent introduces an additional metallization layer between the logic elements and the bond pad vias/through silicon vias. This extra dimensional layer allows the logic elements to be positioned at a different pitch than the underlying via structures, enabling tighter spacing of logic elements without compromising the simplified alignment and bonding of the via layers.
Solution Approach 2:
The patent employs an intermediary metallization structure that acts as a mediator between the logic elements and the bond pad vias/through silicon vias. This intermediary layer decouples the pitch requirements of the logic elements from the pitch constraints of the via structures, allowing independent optimization of both.
2Productivity
If bond pad via pitch is reduced to increase component density, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
By adding a metallization layer in between, the patent creates an additional dimensional degree of freedom. This allows the bond pad vias to maintain a larger, easier-to-manufacture pitch while the logic elements can be densely packed at a smaller pitch through the intermediary metallization structure.
Solution Approach 2:
The intermediary metallization structure serves as a buffer that absorbs the pitch difference between the bond pad vias and the logic elements. This mediator allows independent optimization of via pitch for manufacturing ease and logic element pitch for density, without directly coupling their precision requirements.
3Ease of manufacture
If through silicon via pitch is increased to simplify manufacturing, then ease of manufacture improves, but device active area utilization decreases
Solution Approach 1:
The patent utilizes an additional metallization dimension to decouple the pitch of through silicon vias from the pitch of logic elements. This allows the via pitch to be optimized for manufacturing simplicity while the logic element pitch can be optimized for maximum area utilization through the intermediary metallization layer.
Solution Approach 2:
The metallization structure acts as an intermediary that bridges the pitch mismatch between widely-spaced through silicon vias and densely-packed logic elements. This mediator enables the via structures to maintain larger spacing for easier fabrication while logic elements achieve tighter spacing for better area utilization.
Data Source
AI summary
A bonded die assembly includes first conductive pads of a first substrate each bonded to respective second conductive pads of a second substrate, the first and second conductive pads arrayed at an inter-pad spacing, a plurality of active components located in the second substrate and arrayed at an inter-component spacing, and a metallization structure disposed between the first substrate and the second substrate, where the metallization structure is configured to decrease the inter-component spacing relative to the inter-pad spacing. The die assembly is characterized by an improved utilization of available device active area.