Metallization Structure for One-Sided Vertical MOSFET Packaging
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Solution Overview
Problem
Vertical transistor devices, such as Power MOSFETs, face challenges in packaging due to the need for electrical connections on opposing surfaces, which increases the package size and complexity, making it difficult to achieve low drain-to-source resistance (RDS(on)) using wafer level chip scale packaging techniques.
Innovation Solution
A semiconductor device with a metallization structure comprising multiple conductive layers and insulating layers on a common surface, allowing for direct re-wiring on the chip with pads for external connections, eliminating the need for separate packaging and reducing the footprint by positioning all contacts on one side, thereby minimizing the Si area required for re-wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical connections are supplied to both sides of the vertical transistor device, then low drain to source resistance is achieved, but the package size and complexity increase
Solution Approach 1:
The patent transitions from a two-sided connection architecture to a one-sided connection architecture by stacking source, drain, and gate contacts vertically on the same surface of the semiconductor die. This dimensional reorganization allows all external electrical connections to be accessed from a single surface, eliminating the need for opposing surface connections while maintaining low resistance performance.
Solution Approach 2:
The patent implements a nested contact structure where source, drain, and gate contacts are arranged in concentric or nested patterns on the same surface. The source contact is positioned centrally, with drain and gate contacts surrounding it in a nested configuration, allowing all contacts to be accessed from the top surface without requiring backside connections.
2Reliability
If through silicon via is used to electrically couple the drain region to the drain contact on the opposing surface, then electrical connection is achieved, but the manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the through silicon via structure from the design by reconfiguring all contacts to reside on the same surface. This removes the need for complex via formation processes, backside thinning, and alignment operations required for through-silicon connections, significantly simplifying manufacturing while maintaining electrical coupling functionality.
3Reliability
If vertical transistor device structure is used, then low RDSon is achieved, but the package footprint increases
Solution Approach 1:
The patent utilizes the vertical dimension of the die surface to stack multiple contacts (source, drain, gate) in a layered configuration rather than spreading them out horizontally. This vertical stacking approach minimizes the horizontal footprint while preserving the vertical transistor structure necessary for low RDSon performance.
Data Source
AI summary
In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.