Metallization Via Structure With Planarization for Low-Resistance Routing
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Solution Overview
Problem
Metallization structures in electronic devices suffer from issues such as increased resistance, short circuiting, and cross-talk due to imperfections in the base conductive layer, leading to reduced functionality and efficiency.
Innovation Solution
The formation of uniform conductive vias with vertical profiles is achieved by using specific dielectric layers to prevent the formation of pillar defects, thereby reducing resistance and preventing short circuiting and cross-talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metallization structures are formed on a rough base conductive layer surface, then the manufacturing process is simpler, but pillar defects form causing increased resistance, short circuiting, and cross-talk
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (dielectric material layer) over the rough base conductive layer surface before forming the conductive vias. This pre-planarization step eliminates surface irregularities such as hillocks and raised areas that would otherwise cause pillar defects, ensuring uniform via formation and preventing short circuiting and cross-talk while maintaining manufacturing feasibility
Solution Approach 2:
The patent introduces a dielectric material layer as an intermediary between the rough base conductive layer and the conductive via structures. This intermediary layer acts as a buffer that absorbs surface irregularities, providing a flat formation surface for subsequent via holes and preventing conductive material from forming unintended pillars that would cause electrical defects
2Manufacturing precision
If multiple successive steps are used to form metallization structures, then manufacturing precision is improved, but manufacturing complexity and time increase
Solution Approach 1:
The planarization layer is formed in advance before via hole formation, consolidating the surface preparation step into a single preliminary action. This approach maintains the precision benefits of multiple steps while reducing overall process complexity by establishing a flat surface early, which then simplifies subsequent via formation operations
Solution Approach 2:
The manufacturing process is segmented into distinct functional stages: first forming the planarization layer to address surface irregularities, then forming via holes through the planarized surface, and finally filling with conductive material. This segmentation allows each step to be optimized independently while maintaining overall process efficiency and precision
Data Source
AI summary
An electronic device (e.g., semiconductor packages, semiconductor devices, semiconductor dice, semiconductor components, etc.) includes metallization or conductive layers that are stacked on non-conductive layers to define electrical pathways through the electronic devices, as well as methods of manufacturing the same. The metallization structures are at least directed to formation of uniform conductive or metal vias of the metallization structure, and to reduce resistance to improve transportation of an electrical signal through the one or more embodiments of the metallization structures of the present disclosure. For example, the metallization structures may include one or more metallization or conductive layers and one or more non-conductive layers that are stacked on one another to provide electrical pathways with reduced resistance to improve electrical performance of the metallization structures.