Metallized TSVs in Scribe Lanes for Compact PoP Devices
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Solution Overview
Problem
Package-on-package (PoP) technology faces challenges in reducing the size of packaged silicon dies to enhance integration and efficient use of PCB space, while increasing package size for connections increases costs due to material usage and reduces the number of packages in an assembly lot.
Innovation Solution
The implementation of metallised through silicon vias (TSVs) in scribe lanes between die to create electrical connections between the front-side and rear-side of silicon dies, with metallisation layers extending into scribe lanes to form capture pads for TSVs, allowing for compact PoP devices without occupying costly substrate real estate and enabling reduced die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If package size is increased to facilitate package-to-package connections, then connection reliability is improved, but package cost increases due to increased material usage and reduced number of packages in an assembly lot
Solution Approach 1:
The invention extracts the connection function from the substrate and relocates it to the scribe lane region. By forming capture pads that extend into the scribe lane and creating TSVs in the scribe lane, the connection functionality is separated from the traditional substrate structure, allowing reduced substrate size while maintaining connection reliability.
Solution Approach 2:
The invention transitions from planar connections on the substrate surface to vertical through-silicon via connections in the scribe lane. This dimensional change from 2D substrate surface to 3D vertical vias enables more efficient space utilization and reduces the overall package footprint while maintaining connection integrity.
2Area of stationary object
If package size is reduced to enhance integration and PCB space efficiency, then space utilization is improved, but connection reliability may deteriorate
Solution Approach 1:
The invention segments the connection function into distinct components: capture pads extending into the scribe lane, through-silicon vias for vertical connections, and rear-side metallisation. This segmentation allows each component to be optimized independently, enabling reduced package size while maintaining reliable connections through the specialized scribe lane TSV structure.
3Reliability
If metallisation layers extend into scribe lanes to form capture pads, then electrical connection is improved, but manufacturing complexity increases
Solution Approach 1:
The capture pads are formed as extensions of existing metallisation layers into the scribe lane region during the normal metallisation process, before dicing. This preliminary formation of capture pads integrates the extended connection function into the standard fabrication flow, reducing the need for additional complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables compact, cost-effective, and efficient PoP devices with reduced material usage, lower profile, and lower environmental impact by eliminating the need for bulky BGA substrates, resulting in smaller, more reliable, and lower-cost assemblies.
Implementation Method 1
at least one through substrate via in the scribe lane which electrically connects the at least one metallisation layer on the front-side to the metallisation layer on the rear-side
Implementation Method 2
metallising the at least one through substrate via and at least a portion of a rear-side of the wafer
Data Source
AI summary
Metallized through silicon vias located in the scribe lanes between die are used to create an electrical connection between the front-side and the rear-side of a silicon die. One of the metallization layers on the front-side of the die comprises portions which extend into the scribe lanes to form capture pads for the through silicon vias. The rear-side of the wafer is metallized and this metallization may, in some embodiments, be patterned to form tracks or components. The silicon die may be used to create improved package on package devices. In other examples, other substrate materials may be used.