Debugging Metastability in Digital Circuits via Formal Verification

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Solution Overview

Problem

Traditional methods for debugging metastability issues in digital circuits are inefficient and time-consuming, particularly when dealing with complex semiconductor integrated circuits, as they require repetitive processes to identify culprit clock domain crossing (CDC) pairs causing metastability failures.

Innovation Solution

The implementation of injection modeling and formal verification techniques, where metastability effects are injected into CDC pairs within the cone of influence, allowing for the generation of waveforms to determine which CDC pairs contribute to failures, and applying constraints to remove non-contributory pairs, thereby efficiently identifying problematic CDC pairs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional debugging methods are used to identify culprit CDC pairs, then comprehensive analysis can be performed, but verification time becomes excessively long and debugging efficiency deteriorates

Engineering Contradiction:
Improveidentification accuracy of culprit CDC pairsVSAvoidverification time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The verification process is segmented into two phases: first, generate waveforms for all CDC pairs in the cone of influence to identify potential culprits; second, apply constraints to remove non-contributory CDC pairs and regenerate waveforms only for remaining pairs. This segmentation divides the comprehensive but time-consuming analysis into manageable stages, maintaining identification accuracy while reducing overall verification time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs preliminary waveform generation for all CDC pairs to identify potential culprit pairs before applying constraints. This preliminary action filters out non-contributory CDC pairs in advance, so that subsequent detailed analysis focuses only on the relevant subset, thereby maintaining comprehensive analysis capability while significantly reducing total verification time.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If all CDC pairs in the cone of influence are analyzed, then complete coverage is achieved, but debugging complexity and operational difficulty increase

Engineering Contradiction:
Improvecompleteness of metastability analysisVSAvoiddebugging process simplicity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The method extracts and removes non-contributory CDC pairs from the analysis set by applying constraints based on waveform evaluation. By taking out the irrelevant CDC pairs that do not contribute to metastability failures, the debugging process becomes simpler and more manageable while maintaining complete coverage of all potentially problematic pairs through the initial comprehensive waveform generation.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If repetitive enabling and disabling of CDC pairs is performed to identify culprits, then thorough debugging is achieved, but productivity and verification efficiency decrease

Engineering Contradiction:
Improveaccuracy of culprit identificationVSAvoidverification throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The method performs a preliminary waveform generation step for all CDC pairs to identify potential culprits before applying constraints. This preliminary action creates an initial filter that eliminates non-contributory pairs, so that subsequent verification operations focus only on the relevant subset. This approach maintains accurate culprit identification while significantly improving verification throughput by avoiding repetitive analysis of irrelevant CDC pairs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The verification process is segmented into distinct phases: initial waveform generation for all CDC pairs, constraint application to remove non-contributory pairs, and focused waveform generation for remaining pairs. This segmentation eliminates the need for repetitive enabling and disabling operations, thereby maintaining identification accuracy while improving verification productivity through a more efficient workflow.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11892504B1Method and system for debugging metastability in digital circuits
Publication Date: 2024.02.06 CADENCE DESIGN SYST INC
  • US11892504B1 patent drawing
  • US11892504B1 patent drawing
  • US11892504B1 patent drawing

AI summary

Systems and methods of debugging a design under test for metastability issues using formal verification. In one aspect, the method includes determining, by a server, that a functionality of the DUT failed an assertion; generating, by the server, a plurality of first waveforms for a plurality of clock domain crossing (CDC) pairs that are in a cone of influence of the assertion; applying, by the server, a constraint including a condition to the plurality of waveforms; and generating, by the server, one or more second waveforms for a first subset of the plurality of CDC pairs, wherein the first subset of the CDC pairs satisfied the condition.