Metastability Glitch Detection for Clock and Voltage Faults
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Solution Overview
Problem
Conventional glitch detectors for system-on-chip (SoC) fail to detect clock and voltage glitches effectively due to corruption of reference clock signals and process variations, requiring additional time for voltage glitch detection and being incapable of simultaneous detection of both types of glitches.
Innovation Solution
A glitch detector comprising a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit that generates state signals, reference signals, and glitch signals based on patterns associated with clock and voltage signals, allowing simultaneous detection of clock and voltage glitches without relying on a reference clock signal or trim values, and is independent of process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock glitch detector uses a reference clock signal to detect glitches, then it can identify clock abnormalities, but it fails when the reference clock signal is corrupted
Solution Approach 1:
The patent removes the external reference clock signal from the detection system and replaces it with an internal reference generated by a delay element within the detector itself. This extraction of the vulnerable reference clock input eliminates the security risk of reference corruption while maintaining the ability to detect clock glitches through internal timing comparisons.
Solution Approach 2:
The patent introduces a delay element as an intermediary component that generates an internal reference clock signal by delaying the input clock signal. This intermediary internal reference serves as a mediator between the input clock and the detection logic, enabling glitch detection without direct dependency on the potentially corrupted external reference clock.
2Reliability
If a conventional voltage glitch detector requires trim values from non-volatile memory on start-up, then it can detect voltage glitches, but additional time is required to initiate detection
Solution Approach 1:
The patent performs preliminary calibration of the delay element during manufacturing to establish a fixed delay value that compensates for process variations. This preliminary action eliminates the need for runtime trim value retrieval from non-volatile memory, enabling immediate voltage glitch detection upon system start-up without time-consuming initialization sequences.
Solution Approach 2:
The patent makes the delay element self-calibrating by designing it to automatically compensate for process variations through its inherent circuit characteristics. The delay element serves itself by using its own internal timing properties rather than requiring external trim values, thereby eliminating the time penalty associated with memory retrieval and initialization.
3Device complexity
If a conventional detector is designed to detect only one type of glitch, then it has simple circuitry, but it cannot detect the other type of glitch
Solution Approach 1:
The patent designs a universal glitch detector that can detect both clock and voltage glitches using the same core circuitry. The delay element and detection logic serve multiple functions: they detect clock glitches by monitoring timing violations and simultaneously detect voltage glitches by monitoring their effect on the delay element's timing characteristics, eliminating the need for separate specialized detectors.
Solution Approach 2:
The patent merges the clock glitch detection function and voltage glitch detection function into a single integrated detector. By combining the delay element-based timing reference with voltage monitoring capabilities in one circuit, the patent achieves dual-functionality without proportionally increasing complexity, as both detection modes share the same core timing reference mechanism.
4Ease of manufacture
If process variations cause frequency changes in clock signals, then manufacturing tolerances are accommodated, but conventional detectors fail to distinguish normal variations from actual glitches
Solution Approach 1:
The patent changes the reference parameter from a fixed external clock frequency to a dynamically generated internal reference frequency that is derived from the actual input clock signal through a controlled delay. This parameter change enables the detector to automatically adapt to process-induced frequency variations while maintaining precise glitch detection, as the internal reference scales proportionally with the input clock frequency.
Solution Approach 2:
The patent introduces dynamics into the reference generation process by using a delay element whose output frequency automatically tracks the input clock frequency. This dynamic adaptation allows the detector to distinguish between normal process-induced frequency drift and actual glitch events, as the internal reference continuously adjusts to match the actual operating conditions rather than relying on fixed nominal values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and simultaneous detection of clock and voltage glitches, reducing detection time and eliminating the need for reference clock signals and trim values, while being unaffected by process variations, thereby enhancing the security and reliability of SoC systems.
Implementation Method 1
a metastability detector circuit (202) configured to receive a clock signal and generate a plurality of state signals at each cycle of the clock signal
Data Source
AI summary
A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.