Metastability-Tolerant Signal Calibration Circuit for Compact TDCs
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Solution Overview
Problem
Conventional Time-to-Digital Converters (TDCs) require a large number of flip flops to synchronize samples, leading to significant chip area usage and power consumption, especially as clock periods decrease, due to the inherent metastability of flip flop circuits.
Innovation Solution
The proposed solution involves an independent metastability-tolerant circuit that uses two flip flops with a run clock signal and an XOR gate to detect changes in the output signals, allowing for metastability resolution without the need for multiple synchronizing flip flops, thereby reducing the number of flip flops required and minimizing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip flops are used to synchronize TDC samples, then timing measurement reliability is improved, but chip area and power consumption increase significantly
Solution Approach 1:
The patent extracts the synchronization function from the traditional multi-stage flip-flop cascade and implements it using a single flip-flop with metastability resolution logic. The harmful aspect (excessive chip area) is removed by eliminating redundant flip-flops while preserving the essential synchronization capability through a different architectural approach.
Solution Approach 2:
The patent changes the operational parameters of the flip-flop system by allowing the flip-flop to enter and resolve metastable states rather than preventing them through cascaded stages. This parameter change (from avoiding metastability to resolving it) reduces the number of flip-flops needed from multiple stages to a single stage, significantly reducing chip area.
2Reliability
If conventional flip flops are cascaded to resolve metastability, then synchronization reliability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming cascaded flip-flop structure and replaces it with a single flip-flop配合 metastability resolution logic. This extraction of the synchronization function from the traditional multi-stage approach eliminates the excessive power consumption associated with clocking multiple flip-flops in sequence.
Solution Approach 2:
The patent changes the synchronization approach from preventing metastability (through multiple flip-flops) to resolving it (through a single flip-flop with resolution logic). This parameter change reduces power consumption by eliminating the need to clock multiple flip-flops while maintaining synchronization reliability.
3Area of stationary object
If the number of flip flops is reduced, then chip area and power consumption decrease, but metastability resolution capability is compromised
Solution Approach 1:
The patent introduces metastability resolution logic as an intermediary mechanism between the single flip-flop and the rest of the system. This intermediary logic detects and resolves metastable states, ensuring that the reduced flip-flop count does not compromise reliability. The intermediary compensates for the potential loss of robustness from using fewer flip-flops.
Solution Approach 2:
The patent replaces the mechanical cascade of multiple flip-flops with a different system architecture using a single flip-flop配合 detection and resolution logic. This substitution achieves the same functional goal (metastability resolution) with fewer physical components, reducing chip area while maintaining reliability through a different mechanism.
4Productivity
If clock period is decreased to improve system performance, then productivity increases, but the number of flip flops needed for reliable synchronization increases
Solution Approach 1:
The patent changes the synchronization approach to be independent of clock period through the use of a single flip-flop with metastability resolution logic. This parameter change allows the system to maintain constant synchronization complexity regardless of clock period, enabling high-performance operation without increasing the number of flip-flops even as clock periods decrease.
Data Source
AI summary
This disclosure relates to a circuit comprising a first, second, and third data latch, and an input for a data signal. The first data latch may be configured to sample a delayed version of the data signal in response to a first control signal. The second data latch may be configured to sample the delayed version of the data signal in response to a run clock signal. The run clock signal may be configured to run for a predefined number of clock cycles subsequent to the first control signal. The third data latch may be configured to sample either an output signal of the first data latch or an output signal of the second data latch in response to a second control signal received after the predefined number of clock cycles of the run clock signal.