Metastability-Based Random Number Generator With Adaptive Clocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing random-number generators in computer security are vulnerable due to predictable generation rules, which compromise data security.
Innovation Solution
A true random-number generator comprising delay circuits, sampling circuits, and an operational circuit that adjusts a clock signal and count value based on sampled signals to generate unpredictable random variables, utilizing metastable events to enhance security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional random-number generation methods are used, then the generation process is simple and predictable, but security is compromised due to predictability
Solution Approach 1:
The patent replaces traditional software-based or algorithmic random number generation with a hardware-based physical system that utilizes metastable events in electronic circuits. This substitution of mechanical/physical phenomena for computational methods fundamentally changes the generation mechanism from predictable algorithms to inherently unpredictable physical processes, thereby improving security while accepting increased hardware complexity
Solution Approach 2:
The patent changes the fundamental parameter of randomness generation from algorithmic computation to physical metastable state transitions. By utilizing circuits operating in metastable regions where state transitions are inherently unpredictable and governed by physical noise rather than deterministic logic, the system achieves higher security through parameter transformation
2Reliability
If multiple delay circuits and sampling circuits are added to improve randomness, then unpredictability increases, but device complexity increases
Solution Approach 1:
The patent segments the random number generation process into multiple independent stages: delay circuits that create temporal separation, sampling circuits that capture state transitions, and operational circuits that process samples. Each segment contributes to the overall unpredictability, and the modular segmentation allows the complex function to be distributed across multiple simpler components working in sequence
Solution Approach 2:
The patent employs a nested structure where sampling circuits are embedded within the delay circuit framework, and operational circuits process outputs from multiple sampling stages. The nested arrangement allows each layer to build upon previous layers, with inner sampling circuits capturing refined temporal patterns from outer delay stages, thereby increasing unpredictability through layered processing
3Measurement precision
If the operational circuit adjusts clock signal and count value dynamically, then random variable quality improves, but control complexity increases
Solution Approach 1:
The operational circuit implements feedback mechanisms where the output random variables are monitored and used to adjust the clock signal frequency and count values dynamically. This feedback loop ensures that the random number generator maintains optimal quality by adapting to actual performance characteristics, with the control complexity justified by the significant improvement in random variable precision and security
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution generates highly unpredictable random variables, thereby increasing security by reducing predictability and ensuring robust data protection.
Implementation Method 1
The first delay circuit delays an input signal to generate a first delayed signal. The second delay circuit delays the first delayed signal to generate a second delayed signal.
Implementation Method 2
The first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. The second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. The third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal.
Implementation Method 3
The operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.
Data Source
AI summary
A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.