Method of forming a molded substrate electronic package and structure
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Solution Overview
Problem
The manufacturing of near chip scale packages with small, fine pitch, and small area substrates is challenging due to their thinness and complexity, making it difficult to achieve consistent production while supporting increased functionality and smaller device demands, and existing methods are not cost-effective or efficient for alternative conductive interconnect structures.
Innovation Solution
A method and structure for forming semiconductor packages using a molded substrate with conductive lands separated by grooves, filled with an insulating layer, and topped with conductive patterns formed through electroplating, where the substrate is partially removed to expose bottom land surfaces, allowing for a thin profile and adaptable configurations for attachment to higher assembly levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional plastic encapsulation methods are used for near chip scale packages, then the semiconductor die is protected from hostile environments, but the substrate becomes difficult to manufacture consistently due to thinness and fine pitch requirements
Solution Approach 1:
The substrate is segmented into multiple lands separated by grooves, allowing the encapsulant to be applied in a molded manner that follows the segmented structure. This segmentation enables consistent manufacturing by breaking down the complex fine-pitch substrate into manageable sections that can be reliably formed and protected.
Solution Approach 2:
The lands and grooves are formed on the substrate before encapsulation, creating a pre-structured surface that guides the encapsulant application. This preliminary structuring ensures that the thin substrate maintains its integrity during subsequent manufacturing steps while enabling consistent protection without requiring complex post-encapsulation processing.
2Area of moving object
If the substrate area is reduced to approximate chip size, then the package becomes smaller and more functional, but the manufacturing complexity increases significantly
Solution Approach 1:
The small substrate area is efficiently utilized by segmenting it into multiple functional lands separated by grooves. This segmentation allows each land to serve specific interconnection purposes while the overall compact structure maintains chip-scale dimensions, reducing manufacturing complexity through modular design.
Solution Approach 2:
The substrate design incorporates vertical grooves that create three-dimensional structure within the two-dimensional chip plane. This dimensional transition allows complex interconnect functionality to be achieved without increasing the footprint area, maintaining small package size while managing structural complexity through vertical feature integration.
3Reliability
If traditional conductive interconnect structures are used, then electrical connection is achieved, but the manufacturing process becomes less cost-effective and less efficient
Solution Approach 1:
The lands on the substrate serve dual functions: they provide mechanical support structures and simultaneously serve as self-aligned seed regions for electroplating conductive patterns. This self-service approach eliminates the need for separate alignment and registration processes, reducing manufacturing steps and costs while ensuring reliable electrical interconnection.
Solution Approach 2:
Traditional mechanical alignment methods for forming conductive patterns are replaced with electroplating processes that use the land structures as electrical seeds. This substitution of mechanical alignment with electrochemical deposition simplifies the manufacturing process, improves precision, and reduces costs by eliminating complex alignment machinery and procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation of conductive circuit patterns, enables fine-pitch implementations, reduces manufacturing costs, and facilitates the use of lands as output pads, thereby improving the efficiency and cost-effectiveness of semiconductor package production.
Implementation Method 1
conductive patterns formed through electroplating
Data Source
AI summary
An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.