Metrology-Aware OPC Modeling for Accurate Wafer Pattern Correction
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Solution Overview
Problem
The increasing complexity and density of semiconductor device designs, coupled with light diffraction in optical lithography, lead to inefficiencies and high costs in the design and fabrication process, necessitating a more effective lithography enhancement approach that maintains performance without compromising design quality.
Innovation Solution
A metrology-aware optical proximity correction (OPC) model is introduced to separate lithography effects from metrology errors, allowing for simultaneous training of the OPC and metrology models, thereby reducing computational costs and enhancing modeling accuracy by removing the impact of metrology errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional OPC methods are used to compensate for light diffraction, then lithography enhancement results are improved, but computational cost and processing time increase significantly
Solution Approach 1:
The patent segments the OPC process into multiple iterations with progressively coarser resolution levels. The method performs initial OPC iterations at full resolution, then subsequent iterations at reduced resolution, allowing the process to converge faster while maintaining accuracy where needed.
Solution Approach 2:
The patent implements periodic OPC iterations alternating between full resolution and reduced resolution. This periodic switching allows the system to maintain accuracy during critical convergence phases while reducing computational burden during later stabilization phases.
2Manufacturing precision
If repeated OPC operations are performed across the design layout, then acceptable enhancement results are achieved, but software resource consumption increases
Solution Approach 1:
The patent applies local quality by performing OPC operations selectively on different regions of the layout with different resolution levels. Critical patterns receive full-resolution OPC while less critical areas use reduced-resolution processing, optimizing resource allocation.
Solution Approach 2:
The patent performs partial OPC operations by stopping the iterative process before complete convergence at full resolution, then using reduced-resolution iterations to achieve sufficient enhancement with less computational expense.
3Manufacturing precision
If full-resolution OPC processing is applied to all patterns, then design quality is maintained, but processing efficiency decreases
Solution Approach 1:
The patent dynamically adjusts the resolution level used for OPC processing based on the convergence state and pattern complexity. The system transitions from full-resolution to reduced-resolution processing as the OPC iterations progress, maintaining quality while improving efficiency.
Solution Approach 2:
The patent changes the resolution parameter during the OPC process, starting with full resolution and progressively reducing it in later iterations. This parameter adjustment allows the system to maintain accuracy during critical phases while improving throughput during later phases.
Data Source
AI summary
A method of training model for manufacturing a semiconductor device is provided. Training image data is collected from at least two wafer images on a same wafer. A metrology error function is determined according to the contour difference between at least two wafer images. A metrology-aware correction model including an optical proximity correction (OPC) model and a metrology model is trained based on the metrology error function associated with the metrology model, to obtain a trained OPC model and a trained metrology model.