Metrology System for Overlay Error Prediction and Correction
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Solution Overview
Problem
Current methods for predicting and correcting overlay errors in semiconductor wafer fabrication are complex and unreliable, failing to consistently predict reliable scanner corrections for wafer geometry changes, which affects lithography overlay and critical dimension uniformity.
Innovation Solution
A metrology system using advanced predictive models, such as neural networks, to analyze training wafer geometry and process parameters, selecting optimal sampling strategies, and deploying predictive models to correct overlay errors in real-time during the lithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analytical mechanics models or numerical finite-element models are used to predict overlay errors, then overlay prediction capability is improved, but the physical process complexity increases and reliability decreases
Solution Approach 1:
The patent replaces complex analytical mechanics models and numerical finite-element models with a data-driven machine learning approach. The system uses measured wafer geometry parameters as inputs to train predictive models that output overlay error predictions, substituting physics-based mechanical modeling with statistical learning methods that avoid the complexity of physical process modeling while maintaining prediction accuracy
Solution Approach 2:
The patent creates simplified representations of wafer geometry by measuring specific geometric parameters (such as radius, thickness, flatness) that capture the essential characteristics affecting overlay errors. These measured geometric copies are then used to train predictive models, avoiding the need to model the complete complex physical processes while retaining the critical geometric information needed for accurate overlay prediction
2Measurement precision
If high resolution wafer geometry measurements are used to identify and monitor wafer fabrication processes, then overlay error identification is improved, but measurement and processing time increases
Solution Approach 1:
The patent applies partial measurement by selecting and measuring only the specific wafer geometry parameters that have the most significant impact on overlay errors (such as radius, thickness, and flatness at key locations). Rather than performing complete high-resolution measurements of the entire wafer surface, the system focuses on the critical geometric features that drive overlay variation, thereby reducing measurement and processing time while maintaining prediction accuracy
Data Source
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AI summary
A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.