Mezzanine Interconnect Structure to Reduce BEOL Metal Line Density
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Solution Overview
Problem
Aggressive scaling down of IC dimensions leads to densely spaced gate structures, source/drain contacts, and metal lines, posing challenges in fabricating densely spaced MEOL and BEOL features, which limits further increase in transistor density.
Innovation Solution
The introduction of a mezzanine interconnect layer between MEOL and BEOL features, which includes a metal feature embedded in an etch stop layer, reduces the usage of BEOL features and mitigates the need for increased BEOL feature density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If aggressive scaling down of IC dimensions is pursued, then transistor density increases, but fabrication complexity of densely spaced MEOL and BEOL features increases
Solution Approach 1:
The patent segments the interconnect structure into MEOL (metal-oxide-semiconductor level) and BEOL (back-end-of-line) features, introducing a mezzanine interconnect layer between them. This segmentation allows independent optimization of each layer's fabrication process, reducing the overall fabrication complexity while maintaining high transistor density.
Solution Approach 2:
The mezzanine interconnect layer acts as an intermediary between MEOL and BEOL features. This intermediate layer simplifies the fabrication process by providing a buffer that reduces the need for extremely precise alignment and spacing in the densely spaced BEOL features, thereby reducing fabrication complexity.
2Reliability
If BEOL feature density is increased to accommodate scaling, then interconnect functionality is maintained, but manufacturing costs and process difficulty increase
Solution Approach 1:
The patent introduces a mezzanine interconnect layer that adds a dimensional solution to the density problem. Instead of only increasing BEOL feature density in the planar dimension, the mezzanine layer provides an additional vertical dimension for interconnect routing, maintaining interconnect functionality while reducing manufacturing difficulty.
Solution Approach 2:
The mezzanine interconnect layer effectively creates a copy or duplicate of interconnect functionality at a different level. This allows the BEOL layer to use larger, easier-to-manufacture features while the mezzanine layer provides the necessary dense interconnections, thereby maintaining functionality while improving ease of manufacture.
3Productivity
If the number of metal lines is reduced, then fabrication process is simplified and costs are reduced, but interconnect capacity may be compromised
Solution Approach 1:
The patent merges the interconnect functions of MEOL and BEOL layers through the mezzanine interconnect layer. By combining the advantages of both layers and using the mezzanine layer to bridge them, the design achieves reduced metal line count (improving fabrication efficiency) while maintaining sufficient interconnect capacity through the combined routing capability of all three layers.
Data Source
AI summary
A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.