Mezzanine Interconnect Structure for Dense IC Routing
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Solution Overview
Problem
Aggressive scaling down of IC dimensions leads to densely spaced gate structures, source/drain contacts, and metal lines, posing challenges in fabricating and aligning interconnects, which limits further increase in transistor density.
Innovation Solution
The introduction of a mezzanine interconnect layer between MEOL and BEOL features, comprising a metal feature embedded in an etch stop layer, reduces the usage of BEOL features and alleviates the need for increased BEOL feature density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If aggressive scaling down of IC dimensions is pursued to increase transistor density, then functional density increases, but fabrication and alignment of interconnects becomes increasingly difficult
Solution Approach 1:
The interconnect structure is segmented into multiple layers including MEOL (metal-oxide-semiconductor interconnect layer), BEOL (back-end-of-line interconnect layer), and a mezzanine interconnect layer. This segmentation allows each layer to be optimized independently, with the mezzanine layer handling specific routing functions to reduce the burden on BEOL features and simplify alignment requirements.
Solution Approach 2:
The patent introduces a mezzanine interconnect layer that extends in the first direction (horizontal dimension) between source/drain contacts, creating an additional dimensional pathway for current flow. This reduces the need for densely spaced vertical BEOL vias and metal lines, thereby alleviating alignment complexity while maintaining high transistor density.
2Quantity of substance
If BEOL feature density is increased to accommodate more interconnects, then interconnect capacity increases, but fabrication complexity and costs increase
Solution Approach 1:
The mezzanine interconnect layer acts as an intermediary between the source/drain contacts and the BEOL interconnects. It provides a intermediate routing path that reduces the number of BEOL vias and metal lines needed, thereby maintaining interconnect capacity while reducing fabrication complexity and costs.
Solution Approach 2:
Instead of providing all interconnect capacity through dense BEOL features, the patent uses partial action by implementing a mezzanine layer that handles a portion of the interconnect traffic. This reduces the required BEOL feature density while maintaining overall interconnect capacity.
Data Source
AI summary
A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.